riscv/rocket-chip
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1343 Commits

Author SHA1 Message Date
Andrew Waterman
25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman
80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Henry Cook
d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
solomatnikov
0b9fc94421 Assertion for back-to-back uncached and cached ops (#631) 2017-03-29 23:07:17 -07:00
Megan Wachs
d8033b20fc Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-29 14:58:04 -07:00
Megan Wachs
375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
Megan Wachs
ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Andrew Waterman
8dfbf4532a Use 1 MHz as default timebase (#628) 
Defaulting to 0 prevents Linux from booting
 2017-03-28 19:59:56 -07:00
Andrew Waterman
44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew Waterman
db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew Waterman
4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Megan Wachs
d6ab929c41 debug: Remove older version of JTAG interface as it is superseded by the one in jtag package. 2017-03-27 21:25:37 -07:00
Megan Wachs
bb64c92906 csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again. 2017-03-27 21:21:48 -07:00
Megan Wachs
42ca597478 debug: Breaking change until FESVR is updated as well. 
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
 2017-03-27 21:19:08 -07:00
Megan Wachs
43804726ac tilelink2: more helpful requirement message 2017-03-27 21:05:05 -07:00
Megan Wachs
0c3d85b52b debug: add generated ROM contents and register fields. 2017-03-27 21:01:36 -07:00
Andrew Waterman
05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman
d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman
c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman
069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman
ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
a2a3346e73
 2017-03-27 16:37:09 -07:00
Wesley W. Terpstra
5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
75eba294ec DCache: Release from the correct ID as well 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
4959771c97 Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N" 
This reverts commit 0538dc77ce.
 2017-03-27 16:30:46 -07:00
Wesley W. Terpstra
fa7ead6357 Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO" 
This reverts commit fb6498f2c3.
 2017-03-27 16:30:46 -07:00
Megan Wachs
70fa10fc55 Util: Add ResetCatchAndSync for synchronous deassert of Async Reset (#615) 2017-03-27 03:29:07 -07:00
Megan Wachs
08c4f7cea6 RocketTile: Create a wrapper for SyncRocketTile as well (#616) 
* RocketTile: Create a wrapper for SyncRocketTile as well

There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.

Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.

Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.

It could still be nice to use a parameter vs hard coding "3".

* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
 2017-03-27 02:45:37 -07:00
Megan Wachs
11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice. 
This allows more flexibility e.g. considering the ROM as part of other
devices.
 2017-03-26 20:58:14 -07:00
Megan Wachs
bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. 2017-03-26 20:58:14 -07:00
Megan Wachs
8e6beb80be Add ucb-art/chisel-jtag (#612) 
* jtag: Add ucb-art/chisel-jtag to junctions.

* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch

* jtag: move to a top-level package
 2017-03-26 18:03:21 -07:00
Andrew Waterman
0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew Waterman
e710e32f10 Implement new FP encoding proposal 
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
7180352067 Fix groundtest to provide missing signals to TLB 2017-03-26 14:20:16 -07:00
Andrew Waterman
5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Andrew Waterman
bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Wesley W. Terpstra
537274b645 coreplex: move buffers inside the coreplex 
This should make hierarchical place and route easier.
 2017-03-24 22:54:48 -07:00
Yunsup Lee
5bbb75e078 rename l2FrontendBus as fsb, expose bsb 2017-03-24 22:54:48 -07:00
Henry Cook
996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Wesley W. Terpstra
f36b1766f8 TLROM: use the smallest ROM implementation that works 
The contents everywhere else are still zero.
 2017-03-24 20:40:28 -07:00
Wesley W. Terpstra
ac205ca10a bootrom: move to 0x10000 for more space (DTB on multicore is big) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
34f8ce653a bootrom: follow SBI (a0=hartid, a1=dtb) 2017-03-24 18:18:01 -07:00
Wesley W. Terpstra
9a2f0d01a1 GenerateBootROM: use compiled DTB 2017-03-24 18:18:01 -07:00
Andrew Waterman
17b1ee3037 Default to 8 PMPs; support 0 PMPs 2017-03-24 16:39:52 -07:00
Andrew Waterman
97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM 2017-03-24 16:39:52 -07:00
Andrew Waterman
3f0d2fe826 Instantiate PTW unconditionally 
This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses 2017-03-24 16:39:52 -07:00
Andrew Waterman
ccd5bc9a91 Improve QoR of PMP homogeneity checker 2017-03-24 16:39:52 -07:00
Andrew Waterman
e9cadf29d2 Improve DCache MMIO QoR 
No need to store the cmd field.  From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
fb6498f2c3 Use Reg(Vec) instead of Seq(Reg) for DCache MMIO 2017-03-24 16:39:52 -07:00
Andrew Waterman
0538dc77ce For D$, use source 0 through N-1 for MMIO, not 1 through N 
This makes the code a bit cleaner.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
3951e57789 Force each TLB entry into its own clock-gate group 
This ameliorates a PMP critical path.

I can't figure out how to do this without asUInt/asTypeOf.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
8d7f1d777e Fix an embarrassing typo in the PMPHeterogeneityChecker 2017-03-24 16:39:52 -07:00
Andrew Waterman
10c39cb8d6 Disable mprv in D-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman
d3bda9574c Put page homogeneity checker in PMP 
Avoids redundancy between ITLB and DTLB
 2017-03-24 16:39:52 -07:00
Andrew Waterman
9e05200e51 Don't require that PMP ranges be aligned to access size 
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
29e67279ba add comments 2017-03-24 16:39:52 -07:00
Andrew Waterman
4c8be13a4d Improve homogeneity circuit QoR 2017-03-24 16:39:52 -07:00
Andrew Waterman
59d6afa132 mideleg/medeleg not present without less-privileged traps 2017-03-24 16:39:52 -07:00
Andrew Waterman
38808f55d5 Share PMP mask gen between I$ and D$ 2017-03-24 16:39:52 -07:00
Andrew Waterman
86d84959cf More WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
2888779422 Flush pipeline from WB stage, not MEM 
Fixes sptbr write -> instruction translation hazard.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
44ca3b60ab Retime PTW response valid bits 
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
a03556220c Default TLB size = 32 
@davidbiancolin
 2017-03-24 16:39:52 -07:00
Andrew Waterman
1875407316 Get TLB permission checks off D$ clock gating critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman
a4164348b4 Expose MXR to S-mode 2017-03-24 16:39:52 -07:00
Andrew Waterman
0380aed329 PUM -> SUM 2017-03-24 16:39:52 -07:00
Andrew Waterman
2a413e4496 Remove fruitless debug() 2017-03-24 16:39:52 -07:00
Andrew Waterman
29414f3a23 Simplify interrupt-stack discipline 
f2ed45b179
 2017-03-24 16:39:52 -07:00
Andrew Waterman
723352c3e2 Mitigate some more PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman
7484f27ed3 Don't gate exception-cause pipeline registers separately 
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
 2017-03-24 16:39:52 -07:00
Andrew Waterman
3ea822c2cf Make blocking L1 D$ the default 
The nonblocking cache is overdesigned for most Rocket-class cores, so
the blocking cache is the more appropriate default.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
487b8db5ef Address some PMP critical paths 2017-03-24 16:39:52 -07:00
Andrew Waterman
03fb334c4c Take mprv calculation off critical path 2017-03-24 16:39:52 -07:00
Andrew Waterman
f0796f0509 Pass correct access size information to PMP checker 2017-03-24 16:39:52 -07:00
Andrew Waterman
a6874c03f7 Remove DecoupledTLB 2017-03-24 16:39:52 -07:00
Andrew Waterman
78f9f6b9ef When SFENCE.VMA has rs2 != x0, don't flush global mappings 2017-03-24 16:39:52 -07:00
Andrew Waterman
1b950128e1 PTW should always use S-mode privilege 
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode.  However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.

Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
aace526857 WIP on PMP 2017-03-24 16:39:52 -07:00
Andrew Waterman
b1b405404d Set PRV=M when entering debug mode 
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
 2017-03-24 16:39:52 -07:00
Andrew Waterman
cf168e419b Support SFENCE.VMA rs1 argument 
This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
 2017-03-24 16:39:52 -07:00
Henry Cook
797c18b8db Make some requirement failures more verbose (#608) 
* tilelink: verbose requires in xbar

* diplomacy: verbose requires
 2017-03-23 21:55:11 -07:00
Wesley W. Terpstra
bd08f10816 tilelink2: make sink ids optional (#607) 
* tilelink2: make sink ids optional

* CacheCork: add a special-case for 1 sink id
 2017-03-23 18:19:04 -07:00
Wesley W. Terpstra
19eb9b6906 l1tol2: put a flow Q on the exits (#606) 
This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
 2017-03-23 16:28:32 -07:00
Henry Cook
055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) 2017-03-22 14:38:33 -07:00
Andrew Waterman
76f083b469 FIFOFixer: Not all D-channel messages are A-channel responses 2017-03-21 14:17:38 -07:00
Andrew Waterman
3609254e4a There's no structural hazard on MMIO store responses 
So don't stall as though there were.
 2017-03-21 14:17:32 -07:00
Yunsup Lee
5eae7e1da4 make DCache s1_nack less conservative for pipelined MMIO requests 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4c00066746 rocket: describe dcache as two clients (fifo+cached) 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
81d717e82f coreplex: guarantee FIFO for those tiles that need it 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
198afddb4b tilelink2: add the FIFOFixer 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
930438adba tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
fd521c56a6 tilelink2: add client-side FIFO parameterization 2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4eef317e84 RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E 2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
04892fea01 Monitor: support early ack 2017-03-20 14:49:19 -07:00
Wesley W. Terpstra
278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
778e189bba Monitor: ProbeAckData and ReleaseData may carry an error 2017-03-20 11:44:13 -07:00
Wesley W. Terpstra
48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
0c92283a61 rocket icache: tie off b ready 2017-03-19 17:18:50 -07:00