debug: Fixes in how the SimDTM was hooked up to FESVR

2017-03-28 21:13:45 -07:00
parent ff38ebdf5e
commit ca9a5a1cf7
3 changed files with 12 additions and 12 deletions
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@ -70,7 +70,7 @@ class SimDTM(implicit p: Parameters) extends BlackBox {
  def connect(tbclk: Clock, tbreset: Bool, dutio: uncore.devices.ClockedDMIIO, tbsuccess: Bool) = {
    io.clk := tbclk
    io.reset := tbreset
-    dutio <> io.debug
+    dutio.dmi <> io.debug
    dutio.dmiClock := tbclk
    dutio.dmiReset := tbreset