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288 Commits

Author SHA1 Message Date
Henry Cook d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
Henry Cook ddaeedf2d0 coreplex: make HasTiles more generic 
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
 2017-12-20 17:18:55 -08:00
Wesley W. Terpstra 18b8a61775 Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
Wesley W. Terpstra b8098d18be
diplomacy: remove the :=? operator in favour of magic :*=* (#1139) 
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
 2017-12-01 18:28:37 -08:00
Wesley W. Terpstra 8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Wesley W. Terpstra fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra 7a1937242a coreplex: provide correct bus-width for ITIM blockers 2017-11-18 14:32:37 -08:00
Henry Cook b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Wesley W. Terpstra 0cfa801bfc
coreplex: allow MMIO to be misaligned (#1103) 2017-11-10 15:12:28 -08:00
Wesley W. Terpstra a061b16ee3
coreplex: fix typo (#1104) 2017-11-10 15:11:56 -08:00
Henry Cook d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Wesley W. Terpstra 16116991e7
Fix stateless caching (#1084) 
* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.
 2017-11-01 11:05:56 -07:00
Wesley W. Terpstra a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra 41705808dd Bus: remove deprecated crossing attach methods 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra eeb11a2693 coreplex: eliminate dead code 2017-10-27 01:13:35 -07:00
Wesley W. Terpstra e12bdfdf9b coreplex: attach example external interrupts (#1076) 
Fixes #1071
 2017-10-27 01:12:42 -07:00
Wesley W. Terpstra 13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074) 2017-10-26 23:39:56 -07:00
Wesley W. Terpstra 1d8e539362 coreplex: confirm crossings actually cross the right boundary 2017-10-26 15:53:01 -07:00
Wesley W. Terpstra 9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile 2017-10-26 13:58:52 -07:00
Wesley W. Terpstra 380cc6f03b axi4: now also supports the island pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra ce2b904b19 coreplex: tidy up interrupt crossings 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra e30906589f coreplex: refactor crossings to use node pattern 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 8c5e8dd071 coreplex: leverage improved := composition 2017-10-26 13:04:32 -07:00
Henry Cook b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry Cook 9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry Cook 95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Wesley W. Terpstra 2175758050 interrupts: implement in crossing wrapper 2017-10-26 13:04:29 -07:00
Wesley W. Terpstra c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Wesley W. Terpstra 6bc9c9fc6c coreplex: add a crossing wrapper to generalize the island pattern 2017-10-25 16:56:50 -07:00
Wesley W. Terpstra 82b1aa8116 coreplex: print the A first to look nicer 2017-10-18 16:52:35 -07:00
Wesley W. Terpstra a1ac23d7ec coreplex: continue to print the device name in the address map 2017-10-18 16:44:53 -07:00
Richard Xia 5a951799aa Add atomics support to DTS JSON file. 2017-10-18 15:17:53 -07:00
Wesley W. Terpstra 8b58327fa4 axi4: conversion from TL does not need beatBytes (#1051) 
We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
 2017-10-12 16:41:54 -07:00
Henry Cook b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Megan Wachs 7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Henry Cook 60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook 1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Henry Cook 37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook 660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Andrew Waterman 36c39d01e4 Factor out most of HasRocketTiles into HasTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 70a4127cb8 Factor out some of HaveRocketTiles into HaveTiles 2017-10-07 17:36:24 -07:00
Andrew Waterman 71205b70cc Make RocketTileWrapper a BaseTile 2017-10-07 17:36:24 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Andrew Waterman 32fda51a2c Get rid of paddrBits from SystemBus (#1029) 2017-10-04 12:11:37 -07:00