Wesley W. Terpstra 16116991e7

Fix stateless caching (#1084) ...

* tilelink: ToAXI4 should format it's error message

* WithStatelessBridge: mark the memory bus incoherent and cacheable

... and hope that the user doesn't put more than one master down.

2017-11-01 11:05:56 -07:00

..

BaseCoreplex.scala

coreplex: RocketTileWrapper now HasCrossingHelper

2017-10-26 13:04:32 -07:00

Configs.scala

Fix stateless caching (#1084)

2017-11-01 11:05:56 -07:00

CrossingWrapper.scala

CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074)

2017-10-26 23:39:56 -07:00

FrontBus.scala

TLBuffer: replace TLBufferChain with TLBuffer.chain

2017-10-26 13:04:32 -07:00

InterruptBus.scala

coreplex: attach example external interrupts (#1076)

2017-10-27 01:12:42 -07:00

MemoryBus.scala

diplomacy: use new node style chaining

2017-10-28 11:34:16 -07:00

PeripheryBus.scala

diplomacy: use new node style chaining

2017-10-28 11:34:16 -07:00

Ports.scala

diplomacy: use new node style chaining

2017-10-28 11:34:16 -07:00

ResetVector.scala

tile: remove global Field ResetVectorBits

2017-09-08 14:50:59 -07:00

RocketCoreplex.scala

rocket: clarify intent of boundaryBuffers and move to RocketTile

2017-10-26 13:58:52 -07:00

RTC.scala

diplomacy: change API to auto-create node bundles => cross-module refs

2017-09-22 15:01:39 -07:00

SystemBus.scala

Bus: remove deprecated crossing attach methods

2017-10-28 11:34:16 -07:00