Jacob Chang
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aae9b23036
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Update with paratermized LazyModule
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2016-12-12 16:16:56 -08:00 |
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Jacob Chang
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762afcd54a
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Merge remote-tracking branch 'origin/master' into jchang_test
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2016-12-09 16:56:49 -08:00 |
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Jacob Chang
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4c3083c181
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Remove unnecessary val
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2016-12-09 16:44:30 -08:00 |
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Wesley W. Terpstra
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09afbbafdb
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ahb: weaken RegisterRouter assertion
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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588b944ed4
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ahb: implement and test address decoding
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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5d1064fcb1
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ahb: include a unit test
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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51dfb9cb06
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ahb: TileLink master
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2016-12-08 18:00:39 -08:00 |
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Wesley W. Terpstra
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01b0f6a52b
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ahb: new diplomacy-based AHB bus definition
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2016-12-08 18:00:39 -08:00 |
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Jacob Chang
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54cc071a64
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Fix Fragmenter to ensure logical operations must be sent out atomically.
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
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2016-12-07 16:22:05 -08:00 |
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Wesley W. Terpstra
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1bd8a2e239
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Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections
Parameterize diplomatic connections
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2016-12-07 15:03:53 -08:00 |
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Wesley W. Terpstra
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c2eedbfe23
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tilelink2 Monitor: use Parameters instead of global variables
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2016-12-07 12:24:03 -08:00 |
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Wesley W. Terpstra
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020fbe8be9
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diplomacy: make config.Parameters available in bundle connect()
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
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2016-12-07 12:24:01 -08:00 |
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Andrew Waterman
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915697cb09
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Fix FEQ flag generation (#479)
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
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2016-12-06 11:54:29 -08:00 |
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Wesley W. Terpstra
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fbfa15efea
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TLBroadcast: support non-FIFO devices (#482)
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2016-12-05 22:10:37 -08:00 |
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Wesley W. Terpstra
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3c9718ec8f
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clint: undefined registers must be zero (#480)
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
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2016-12-05 17:11:53 -08:00 |
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Henry Cook
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f3d0692619
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Make a directory for the config package (#464)
* [config] make dir structure mirror packages
* [config] expunge max_int
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2016-12-05 10:42:16 -08:00 |
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Henry Cook
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d0a0c887dc
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[tracegen] decrease default address bag size (#462)
while increasing the default number of requests.
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2016-12-04 22:46:55 -08:00 |
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Schuyler Eldridge
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36fe024671
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CacheName no longer needed in RoCCInterface
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
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2016-12-04 19:01:39 -08:00 |
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Schuyler Eldridge
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624db2034b
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Make instantiated RoCC use dcacheParams
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2016-12-04 19:01:39 -08:00 |
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Henry Cook
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9fb7934a37
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WIP PR to figure out why travis is failing (#471)
Make travis use a docker image with pre-built toolchain and verilator
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2016-12-04 13:10:13 -08:00 |
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Jacob Chang
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9ac78a0d37
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Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
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2016-12-02 14:21:36 -08:00 |
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Jacob Chang
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e8d3b647f2
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Removed val from case class for Parameters
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2016-12-02 14:21:15 -08:00 |
|
Jacob Chang
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053f81d7c6
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minor Changes needed to support formal tests
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2016-12-02 14:21:15 -08:00 |
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Jacob Chang
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aa39b3d09d
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Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
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2016-12-01 18:37:13 -08:00 |
|
Jacob Chang
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be23189f77
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Removed val from case class for Parameters
|
2016-12-01 18:36:18 -08:00 |
|
Jacob Chang
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6d402ff1af
|
minor Changes needed to support formal tests
|
2016-12-01 18:36:18 -08:00 |
|
Jacob Chang
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60889df576
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Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
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2016-12-01 15:17:30 -08:00 |
|
Jacob Chang
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cff2612cdb
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minor Changes needed to support formal tests
|
2016-12-01 15:02:23 -08:00 |
|
Jacob Chang
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a49b6d6569
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Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests
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2016-12-01 15:01:52 -08:00 |
|
Jacob Chang
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5e9496fd14
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minor Changes needed to support formal tests
|
2016-12-01 14:56:16 -08:00 |
|
Jacob Chang
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75512e9aa0
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minor Changes needed to support formal tests
|
2016-12-01 14:55:25 -08:00 |
|
Henry Cook
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4234cff074
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Merge pull request #444 from ucb-bar/bump-submodules
rocketchip: bump all submodules (and remove cde)
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2016-11-29 00:13:00 -08:00 |
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Henry Cook
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131659cc2a
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Merge branch 'master' into bump-submodules
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2016-11-28 16:20:42 -08:00 |
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heinzbeinz
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d07e30ba97
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Update README.md
fixed torture link
|
2016-11-28 16:19:09 -08:00 |
|
Henry Cook
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a8ee7e0678
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Update README
|
2016-11-28 16:10:50 -08:00 |
|
Yunsup Lee
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18d100c2b5
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Merge pull request #461 from ucb-bar/sifive-copyright
Sifive copyright
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2016-11-28 15:25:33 -08:00 |
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Henry Cook
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86065e5fb8
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Merge remote-tracking branch 'origin/master' into bump-submodules
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2016-11-28 13:49:59 -08:00 |
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Wesley W. Terpstra
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b7963eca4e
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copyright: ran scripts/modify-copyright
|
2016-11-27 22:15:43 -08:00 |
|
Wesley W. Terpstra
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d4708694ea
|
scripts/authors: Matthew Naylor's submissions were under Berkeley terms
|
2016-11-27 22:15:43 -08:00 |
|
Wesley W. Terpstra
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e2ec1d00ad
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copyright: normalize /// to // in comments
|
2016-11-27 22:15:43 -08:00 |
|
Wesley W. Terpstra
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a0e10aec05
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uncore: removed obsolete Builder file
|
2016-11-27 22:15:43 -08:00 |
|
Wesley W. Terpstra
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8510d9e697
|
scripts: two scripts to determine copyright holder of files
|
2016-11-27 22:15:38 -08:00 |
|
Wesley W. Terpstra
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4146f6a792
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TLB: do not access illegal addresses (#460)
|
2016-11-26 15:11:42 -08:00 |
|
Richard Xia
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97a853a995
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Merge pull request #459 from ucb-bar/bump-chisel-for-firrtl-jar-gitignore
Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
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2016-11-26 13:55:53 -08:00 |
|
Richard Xia
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4e3682f889
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Bump chisel3 by just one commit to pull in gitignore for firrtl.jar.
|
2016-11-26 12:24:10 -08:00 |
|
Wesley W. Terpstra
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a17753983a
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coreplex: allow legacy devices to override the config string (#458)
|
2016-11-25 19:38:24 -08:00 |
|
Wesley W. Terpstra
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9433da8458
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Merge pull request #457 from ucb-bar/jtag-depth-1
Jtag depth 1
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2016-11-25 18:41:39 -08:00 |
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Wesley W. Terpstra
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233280e7d2
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AsyncBundle: save a wasted bit when depth=1
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2016-11-25 18:11:01 -08:00 |
|
Wesley W. Terpstra
|
d755edffcc
|
DebugTransport: use ToAsyncDebugBus for correct depth
|
2016-11-25 18:10:28 -08:00 |
|
Wesley W. Terpstra
|
2b80386a9e
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rocketchip: TileInterrupts needs a TLCacheEdge (#456)
|
2016-11-25 17:02:29 -08:00 |
|