Andrew Waterman
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a94b4af92d
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Simplify AsyncResetRegVec and make AsyncResetReg companion object
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2016-09-16 11:25:10 -07:00 |
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Wesley W. Terpstra
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dd19e0911e
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tilelink2: handle bus width=1
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2016-09-15 22:15:11 -07:00 |
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Wesley W. Terpstra
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e1d7f6d7df
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PRCI: always use bus width >= XLen
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2016-09-15 22:15:07 -07:00 |
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Wesley W. Terpstra
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0e80f7fd0f
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HintHandler: don't violate Irrevocable rules
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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f05222a072
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testconfigs: disable atomics until AtomicAbsorber finished
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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38a9421c75
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Comparator: don't compare addr_beat when it's irrelevant
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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669e3b0d96
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Regression: fix-up address lookup
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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30fa4ea956
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RegisterRouter: compress register mapping for sparse devices
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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6b1c57aedc
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tilelink2: compute minimal decisive mask
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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fb24e847fd
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rocketchip: globals are for sissies
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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644f8fe974
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rocketchip: switch to TL2 mmio + port PRCI
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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91e7da4de3
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tilelink2: make RegisterRouter constructor args public
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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3875e11b26
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tilelink2: RegField splits up big registers
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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5c8e52ca32
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devices: TL2 version of ROM
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2016-09-15 21:28:56 -07:00 |
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Wesley W. Terpstra
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3f30e11f16
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tilelink2: Legacy, manager_xact_id does not matter for uncached
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2016-09-15 21:28:55 -07:00 |
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Wesley W. Terpstra
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ddd93871d8
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tilelink2: add an executable manager parameter
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2016-09-15 21:28:55 -07:00 |
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Wesley W. Terpstra
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9442958d67
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tilelink2: allow := on nodes outside the tilelink2 package
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2016-09-15 21:28:55 -07:00 |
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Jack Koenig
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f2fe437fa4
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Use CDEMatchError for improved performance (#304)
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2016-09-15 19:47:18 -07:00 |
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Henry Cook
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0a65238920
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Merge branch 'master' into tl2-irrevocable
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2016-09-15 10:30:50 -07:00 |
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Howard Mao
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49863944c4
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merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer
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2016-09-14 21:36:27 -07:00 |
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Howard Mao
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f363f5f709
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wrap TestHarness latency pipe in module
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f5db83a72f
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NTiles should not be a Knob
|
2016-09-14 21:16:54 -07:00 |
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Howard Mao
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646527c88e
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use named constants to set AXI resp, cache, and prot fields
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2016-09-14 21:16:54 -07:00 |
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Howard Mao
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f95b8c4ec2
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move UnitTest back into rocketchip module
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2016-09-14 20:51:56 -07:00 |
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Henry Cook
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cde104b3fa
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[junctions] Removes the obsoleted SMI.
Closes #280.
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2016-09-14 20:06:22 -07:00 |
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Henry Cook
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ab3814dcee
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Merge branch 'master' into tl2-irrevocable
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2016-09-14 19:00:17 -07:00 |
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Yunsup Lee
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e404bea2ee
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Merge branch 'master' into move-bootrom
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2016-09-14 18:58:48 -07:00 |
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Wesley W. Terpstra
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1c7d7f9d32
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tilelink2 RegisterRouterTest: stall on both edges
|
2016-09-14 18:22:12 -07:00 |
|
Yunsup Lee
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97809b183f
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refactor unittest framework
as a result, there's another SUITE that needs to run
|
2016-09-14 18:10:21 -07:00 |
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Henry Cook
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d35060b881
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[junctions] messed up the merge lulz
|
2016-09-14 17:55:16 -07:00 |
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Henry Cook
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1b53e477fa
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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Henry Cook
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e02d149cbe
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Henry Cook
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08c4c7b985
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[junctions] make async crossings capable of providing IrrevocableIO
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2016-09-14 17:38:54 -07:00 |
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Megan Wachs
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1308680f75
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Add some async/clock utilities
|
2016-09-14 16:30:59 -07:00 |
|
Yunsup Lee
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710f1ec020
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Move BootROM from Coreplex to Periphery
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2016-09-14 16:09:59 -07:00 |
|
Henry Cook
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aa3fa90fe3
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[tilelink2] Monitor: miscopied name in assert message
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2016-09-14 14:56:50 -07:00 |
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Henry Cook
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d76e19a6ab
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[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
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2016-09-14 14:23:23 -07:00 |
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Andrew Waterman
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565444c40e
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Make UnitTestCoreplex cope with an external MMIO network
|
2016-09-14 12:19:21 -07:00 |
|
Andrew Waterman
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5828e6042e
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Work around https://github.com/ucb-bar/firrtl/issues/299
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2016-09-14 11:47:10 -07:00 |
|
Andrew Waterman
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c3ddff809b
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Move PRCI from Coreplex to always-on block, where it belongs
|
2016-09-14 11:01:05 -07:00 |
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Andrew Waterman
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5566bf1b13
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Don't route PLIC interrupts through PRCI
The PLIC is local to the Coreplex, and PRCI should not be.
|
2016-09-14 11:01:05 -07:00 |
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mwachs5
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47acbf928b
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Give AsyncCrossing slave interfaces registers visibility into when they were written (#288)
|
2016-09-14 00:17:26 -07:00 |
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Howard Mao
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bdb7b1de36
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move tilelink-agnostic counters from uncore to util package
|
2016-09-13 20:47:05 -07:00 |
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Howard Mao
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1882241493
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move junctions utils into top-level utils package
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2016-09-13 20:47:04 -07:00 |
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Henry Cook
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7dd4492abb
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First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
|
2016-09-13 20:30:14 -07:00 |
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Wesley W. Terpstra
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d23ab7370d
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tilelink2: Unit Test for the RegisterCrossing
|
2016-09-13 18:33:56 -07:00 |
|
Wesley W. Terpstra
|
cc88bf1b08
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junctions: give unit tests more time
|
2016-09-13 18:33:56 -07:00 |
|
Wesley W. Terpstra
|
acedd3688a
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tilelink2: unit test for the clock crossing
|
2016-09-13 18:33:56 -07:00 |
|
Wesley W. Terpstra
|
c8e6d47884
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tilelink2: add a clock crossing adapter
|
2016-09-13 18:33:56 -07:00 |
|
Wesley W. Terpstra
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44501cdbf8
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crossings: change defaults to sync=3 for safer settling time
Make the matching AsyncQueue depth=8 to support full throughput
|
2016-09-13 18:33:56 -07:00 |
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