riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
458 Commits 1 Branch 0 Tags
a44e054c77cd23e2666890ddc15ecbf316c03642
Commit Graph

458 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Yunsup Lee 91f211f766 updates to README 2014-10-07 02:08:03 -07:00
Yunsup Lee 702ddabe26 add ExampleSmallConfig for README 2014-10-07 02:07:59 -07:00
Yunsup Lee ae9b78d9ef add what/how explanation to README 2014-10-07 02:07:39 -07:00
Scott Beamer 5f55ded723 bump fpga submodule 2014-10-06 13:45:12 -07:00
Scott Beamer 06bc6a45db move fpga repo to git@ from https 2014-10-06 13:45:09 -07:00
Henry Cook 23ae6893ad bump chisel 2014-10-06 13:45:03 -07:00
Yunsup Lee e25d420155 Improve ChiselConfig composability; bump chisel 2014-10-06 13:43:40 -07:00
Yunsup Lee 73eac94a65 Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays) 2014-10-06 13:40:35 -07:00
Henry Cook f97a801d60 Parameter API update 2014-10-06 13:37:42 -07:00
Henry Cook 122733b3a9 file name consistency 2014-10-06 13:37:38 -07:00
Henry Cook a9d72aac2a bump rocket 2014-10-06 13:37:27 -07:00
Henry Cook 0b5f23a209 Streamlined uncore for release 2014-10-06 13:37:15 -07:00
Yunsup Lee 6c18cd9559 add new fpga-zynq as submodule 2014-09-30 09:32:02 -07:00
Yunsup Lee 7a28d2b47c forgot to move more hwacha stuff out in rocket-chip 2014-09-25 15:34:18 -07:00
Yunsup Lee 70b0f9fd4d error out for PCWM-L, port width mismatch 2014-09-25 06:50:50 -07:00
Adam Izraelevitz 15fb4730ec Add BuildTile parameter for Tile 
Conflicts:
	rocket
 2014-09-25 06:50:45 -07:00
Henry Cook 7398b00d93 dir supplied by function 2014-09-25 06:50:41 -07:00
Henry Cook db4de7b806 bump chisel 2014-09-25 06:50:36 -07:00
Henry Cook 5a840c5520 support for multiple tilelink paramerterizations in same design 2014-09-25 06:50:30 -07:00
Yunsup Lee e2ed81dcd2 push chisel 2014-09-25 06:50:05 -07:00
Donggyu Kim eb384f6461 new RocketChipBackend implementation 2014-09-25 06:47:12 -07:00
Scott Beamer f2ca887de3 better fpga configs 2014-09-25 06:47:03 -07:00
Donggyu Kim 4fe48f5a0a bump chisel 2014-09-25 06:46:58 -07:00
Donggyu Kim 60d90f5230 recover collectNodesIntoComp in Backends.scala 2014-09-25 06:46:50 -07:00
Donggyu Kim a53091b40f remove collectNodesIntoComp from Backends.scala 2014-09-25 06:46:27 -07:00
Scott Beamer 1a101f8de5 don't use latches on mem ports for fpga 2014-09-25 06:46:21 -07:00
Scott Beamer f4e6cd75ab turn off fpu for default fpga config. 
a larger fpga can use defaultconfig
 2014-09-25 06:46:16 -07:00
Stephen Twigg fefa560017 Change addons subproject to use .addons-dont-touch directory instead of addons 
This hides the directory name under standard invocations of ls and thus avoids confusing the user with extra directory names.
 2014-09-25 06:46:06 -07:00
Stephen Twigg 69d765744c Adjustments to the build structure (see below) 
All 'addon' subprojects now have their sources aggregated into the addons subproject. This is done via a source copy (so that sbt will only rebuild sources that actually changed). To prevent caching issues the addons/src directory is CLEARED and then refilled every time addons is compiled. Thus, it is CRUCIAL NO SOURCES ARE MANUALLY ADDED TO addons/src AS THEY WILL BE WIPED BY addons/prepare. Due to sbt source caching, sbt will still be able to tell which sources have changed. (Strangely, sbt would not cache sources in extra unmanaged source directories and thus would always recompile them.) Also, cleaned up project/build.scala a bit to remove some warnings: Added import scala.language/postFixOps (so make! at the bottom no longer errors) and .toURI.toURL (as straight .toURL has been deprecated by the java standard library).
 2014-09-25 06:45:21 -07:00
Yunsup Lee 3b9624277a normalize rocket-chip to reference-chip 2014-09-25 06:45:09 -07:00
Yunsup Lee 6495d0e6f7 bump rocket,uncore 2014-09-17 11:26:12 -07:00
Yunsup Lee 041a362943 push chisel 2014-09-17 11:12:12 -07:00
Yunsup Lee 221007595b allow BACKEND/CONFIG be environment variables 2014-09-17 11:12:08 -07:00
Adam Izraelevitz 484648d9c7 Changed CONFIG from a recursively expanded variable to a conditionally 
assigned variable, allowing users to define CONFIG external to Makefile
 2014-09-17 11:12:02 -07:00
Yunsup Lee ef2e96211c bump chisel/hardfloat/rocket/uncore 2014-09-12 18:10:00 -07:00
Yunsup Lee 09de2e2794 compute number of outstanding misses for DRAMSideLLCNull 2014-09-12 18:09:38 -07:00
Yunsup Lee e40a6fdd64 more tweaks to README 2014-09-12 10:22:00 -07:00
Yunsup Lee c57dea415c fix markdown 2014-09-12 10:18:14 -07:00
Yunsup Lee 1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Stephen Twigg 2367b7beb5 Added logic to sbt so that, for rocketchip, it will automatically include src/main/scala sources from subdirectories into the rocketchip top-level project not already handled by formal subprojects 2014-09-12 01:08:11 -07:00
Yunsup Lee 2c33852c52 final touches 2014-09-12 00:19:29 -07:00
Yunsup Lee 275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee c98afa1fea turn off DRAMSideLLC 2014-09-11 22:10:25 -07:00
Yunsup Lee b5a64487eb turn off DRAMSideLLC 2014-09-11 22:07:44 -07:00
Yunsup Lee 9dfaf5459e bump hardfloat,riscv-tools 2014-09-11 03:08:21 -07:00
Yunsup Lee 5f8bd18fac Makefiles should be perfect 2014-09-11 02:53:46 -07:00
Yunsup Lee bb22ecc8b5 fix rocket interrupt issue 
h/t Andrew
 2014-09-11 02:52:05 -07:00
Yunsup Lee 086bb02c24 check RISCV envirnoment variable 2014-09-11 02:38:21 -07:00
Yunsup Lee 02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00