riscv/rocket-chip
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676 Commits

Author SHA1 Message Date
Andrew Waterman
3b38736a8e Make BaseTopModule and BaseTopModule abstract 
They aren't meant to be directly instantiated.
 2016-09-19 17:18:35 -07:00
Andrew Waterman
d0572d6aab Allow reset vector to be set dynamically 
A chip's power-up sequence, or awake-from-sleep sequence, may wish to
set the reset PC based upon dynamic properties, e.g., the settings of
external pins.  Support this by passing the reset vector to the Coreplex.
ExampleTop simply hard-wires the reset vector, as was the case before.

Additionally, allow MTVEC to *not* be reset.  In most cases, including
riscv-tests, pk, and bbl, overriding MTVEC is one of the first things
that the boot sequence does.  So the reset value is superfluous.
 2016-09-19 17:18:03 -07:00
Andrew Waterman
e6c1bcfedd Expose carry-out bits from WideCounter 2016-09-19 15:54:17 -07:00
Yunsup Lee
1b26d78114 correctly print out the addrmap overlapping error message 2016-09-19 13:34:58 -07:00
Henry Cook
df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
Henry Cook
ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Henry Cook
7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00
Andrew Waterman
a49814c667 Allow WideCounter to not be reset 2016-09-18 18:45:51 -07:00
Wesley W. Terpstra
9817a00ed9 tilelink2: Fuzzer should check address validity before injection 2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1 tilelink2: differentiate fast/safe address lookup cases 2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214 tilelink2: minimize Xbar decode logic 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c tilelink2: consider the implications of negative address mask 2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548 tilelink2: track interrupt connectivity like in TL2 2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
01c1886b9d Utils: cacheable only if there is a cache manager 2016-09-17 00:56:21 -07:00
Wesley W. Terpstra
6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
e749558190 ROM: optionally (default: true) executable 2016-09-17 00:19:09 -07:00
Wesley W. Terpstra
c70045b8b3 Utils: express cacheability from TL2 to TL1 2016-09-17 00:16:40 -07:00
Wesley W. Terpstra
e3d2bd3323 Top: print memory region properties, RWX [C] 2016-09-17 00:16:00 -07:00
Wesley W. Terpstra
5c858685aa Utils: support managers with multiple addresses 2016-09-16 18:03:49 -07:00
Richard Xia
3fdf40c088 Change implicit argument to explicit. 2016-09-16 17:47:31 -07:00
Wesley W. Terpstra
a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
Wesley W. Terpstra
b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Richard Xia
63f13ae7ce Merge remote-tracking branch 'origin/master' into rxia-testharness-refactor 2016-09-16 17:10:52 -07:00
Wesley W. Terpstra
dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
Andrew Waterman
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter 
That's all it's doing (there wasn't much PRC).
 2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
mwachs5
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Wesley W. Terpstra
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
Henry Cook
851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports 2016-09-15 14:25:47 -07:00
Henry Cook
245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
Henry Cook
a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor 2016-09-15 13:27:07 -07:00
Henry Cook
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00
Henry Cook
888f6a2a55 Revert "move UnitTest back into rocketchip module" 
This reverts commit f95b8c4ec2.
 2016-09-15 11:48:09 -07:00
Henry Cook
0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook
ab3814dcee Merge branch 'master' into tl2-irrevocable 2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Wesley W. Terpstra
1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881 [junctions] messed up the merge lulz 2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook
08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman
5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) 2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao
1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00