Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
5d2a470215
|
all rocket-specific arbiters in one file and refactored traits slightly
|
2012-10-15 16:05:32 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
|
2012-10-07 22:20:03 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
e1f9dc2c1f
|
generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
|
2012-05-03 02:29:09 -07:00 |
|
Henry Cook
|
622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
|
eafdffe125
|
simplify page table walker; speed up emulator
|
2012-05-01 01:24:36 -07:00 |
|
Yunsup Lee
|
62ada5ea9e
|
hookup vitlb ptw port
|
2012-03-17 23:01:06 -07:00 |
|
Andrew Waterman
|
6c26921766
|
reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
|
2012-03-16 18:35:54 -07:00 |
|
Yunsup Lee
|
8678b3d70c
|
clean up ioDecoupled/ioPipe interface
|
2012-03-01 20:48:46 -08:00 |
|
Yunsup Lee
|
bfd0ae125e
|
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
|
2012-02-26 23:46:51 -08:00 |
|
Andrew Waterman
|
2d04664a98
|
simplify cpu-cache interface
|
2012-02-26 18:26:29 -08:00 |
|
Yunsup Lee
|
f3bb02b2ea
|
refactored dmem arbiter
|
2012-02-26 17:38:08 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
3045b33460
|
remove second RF write port
load miss writebacks are treated like mul/div now.
|
2012-01-02 02:51:30 -08:00 |
|
Andrew Waterman
|
2f8fcebea0
|
remove datapath register resets resets
|
2012-01-01 16:09:40 -08:00 |
|
Andrew Waterman
|
a8d0cd95e6
|
hellacache now works
|
2011-12-17 03:26:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Rimas Avizienis
|
83d90c4dab
|
more itlb/dtlb/ptw fixes
|
2011-11-12 15:00:45 -08:00 |
|
Rimas Avizienis
|
73416f224b
|
more tlb/ptw debugging
|
2011-11-12 00:25:06 -08:00 |
|
Rimas Avizienis
|
a1ce908541
|
dcache/dtlb overhaul
|
2011-11-11 18:18:47 -08:00 |
|
Rimas Avizienis
|
e4fa94aa27
|
checkpoint
|
2011-11-10 17:41:22 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
62407b4668
|
more tlb/ptw fixes
|
2011-11-10 00:23:29 -08:00 |
|
Rimas Avizienis
|
9aca403aa8
|
more itlb integration & cleanup
|
2011-11-09 23:18:14 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|