24509fc69f
debug_v013: Bump FESVR to pick up minor off-by-1 in error printing code.
2017-03-29 15:20:07 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
f6e72a3ef6
debug: Bump riscv-tools to pick up FESVR to version that works with debug v013
2017-03-29 14:46:06 -07:00
375a039279
debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec)
2017-03-28 21:14:22 -07:00
ca9a5a1cf7
debug: Fixes in how the SimDTM was hooked up to FESVR
2017-03-28 21:13:45 -07:00
ff38ebdf5e
debug: Bump FESVR version to initial Debug v13. Doesn't work yet.
2017-03-28 21:12:57 -07:00
8dfbf4532a
Use 1 MHz as default timebase ( #628 )
...
Defaulting to 0 prevents Linux from booting
2017-03-28 19:59:56 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
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There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
db3ed12ce3
Fix regression in groundtest DummyPTW
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Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
2017-03-28 00:56:14 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
d6ab929c41
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
cbc8d2400a
debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version
2017-03-27 21:24:44 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
42ca597478
debug: Breaking change until FESVR is updated as well.
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* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
0c3d85b52b
debug: add generated ROM contents and register fields.
2017-03-27 21:01:36 -07:00
877e1cfba1
debug: add scripts to generate v13 Debug ROM contents.
2017-03-27 20:51:54 -07:00
ed38787c36
Merge pull request #622 from ucb-bar/priv-1.10
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Various priv-1.10 changes
2017-03-27 19:28:30 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
ab300f7985
Update README_TRAVIS.md
2017-03-27 17:45:50 -07:00
3fc74f3d08
Create README_TRAVIS.md
2017-03-27 17:45:46 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
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This reverts commit 0538dc77ce
2017-03-27 16:30:46 -07:00
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
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This reverts commit fb6498f2c3
2017-03-27 16:30:46 -07:00
861651587b
debug: Update Makefile to use new OpenOCD and allow for easier debugging. ( #619 )
2017-03-27 15:52:04 -07:00
7014263c29
Update LICENSE.SiFive ( #618 )
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Bump the year for the SiFive license
2017-03-27 14:55:28 -07:00
70fa10fc55
Util: Add ResetCatchAndSync for synchronous deassert of Async Reset ( #615 )
2017-03-27 03:29:07 -07:00
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
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* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
722b0d521f
bootrom: also setup SBI a0+a1 for when we hang ( #617 )
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This way a program started by the debugger still has the DTB handy.
2017-03-27 00:01:05 -07:00
11507ac7d6
TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
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This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
bf648514e3
TLROM: allow name and compatibility strings to be provided by subclasses.
2017-03-26 20:58:14 -07:00
8e6beb80be
Add ucb-art/chisel-jtag ( #612 )
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* jtag: Add ucb-art/chisel-jtag to junctions.
* jtag: Add missing Utils file for Tristate and NegativeEdgeLatch
* jtag: move to a top-level package
2017-03-26 18:03:21 -07:00
0e2b780089
Bump hardfloat, giving us the 5th rounding mode finally!
2017-03-26 14:20:16 -07:00
e710e32f10
Implement new FP encoding proposal
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Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
2017-03-26 14:20:16 -07:00
7180352067
Fix groundtest to provide missing signals to TLB
2017-03-26 14:20:16 -07:00
5d1165c850
Express PMP mask generator using a carry chain
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This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
bb42f3bf3b
WIP on FPU subword recoding
2017-03-26 14:20:16 -07:00
986e1754be
Merge pull request #611 from ucb-bar/expose-back-side-bus
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rename l2FrontendBus as fsb, expose bsb
2017-03-24 23:32:50 -07:00
537274b645
coreplex: move buffers inside the coreplex
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This should make hierarchical place and route easier.
2017-03-24 22:54:48 -07:00
5bbb75e078
rename l2FrontendBus as fsb, expose bsb
2017-03-24 22:54:48 -07:00
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
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Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
19485a9861
Merge pull request #609 from ucb-bar/dtb-rom
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DTB in the bootrom
2017-03-24 21:54:13 -07:00
e74226564c
travis: add dependency on device-tree-compiler
2017-03-24 20:59:33 -07:00
f36b1766f8
TLROM: use the smallest ROM implementation that works
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The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
ac205ca10a
bootrom: move to 0x10000 for more space (DTB on multicore is big)
2017-03-24 18:18:01 -07:00
