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Author	SHA1	Message	Date
Wesley W. Terpstra	9655621aa8	Merge pull request #396 from ucb-bar/decoupled ... TL2 Decoupled	2016-10-13 19:09:58 -07:00
Wesley W. Terpstra	4e40f9bb59	tilelink2 Nodes: appease the PC police	2016-10-13 17:02:18 -07:00
Wesley W. Terpstra	54b73aef57	tilelink2: WidthWidget and Fragmenter no longer erase latency	2016-10-13 17:02:18 -07:00
Wesley W. Terpstra	200cf3dd13	tilelink2 Nodes: include some options to test for conformance	2016-10-13 17:02:18 -07:00
Wesley W. Terpstra	5d5b5a66f4	tilelink2 RAMModel: fix a write-bad-data bug	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	e5a1483358	tilelink2 Fragmenter: eliminate most of the registers on A	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	99c7003d11	tilelink2: allow preemption of Fragmenter and WidthWidget	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	b42cfdc9dd	tilelink2 Arbiter: there is only one winner	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	b6e9b0c558	tilelink2 Arbiter: allow preemption of first beat	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	0aebf9e341	tilelink2 ToAXI4: no arbitration path register needed	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	0e897b905f	tilelink2 RegisterRouter: data path register is no longer required	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	c4eadd3ab3	tilelink2 Monitor: enforce stricter transaction ordering	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	d8a1163131	tilelink2 Monitor: don't enforce Irrevocable any more	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	405f66da32	tilelink2 WidthWidget: cope with Decoupled inputs	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	e2e72ac979	tilelink2 Fragmenter: cope with Decoupled input	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	023c6402e9	tilelink2: switch to DecoupledIO syntax	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	980bb3fbfd	Merge pull request #395 from ucb-bar/axi4-fragmenter ... AXI4 fragmenter	2016-10-13 17:01:53 -07:00
Wesley W. Terpstra	4c1c52486b	axi4 Fragmenter: handle more inflight AXI requests than we have space	2016-10-13 15:52:32 -07:00
Wesley W. Terpstra	8005266131	axi4 Fragmenter: refine sideband FSM for case of last fragment	2016-10-13 15:52:32 -07:00
Wesley W. Terpstra	19064e602b	axi4 Fragmenter: align all output accesses ... We promised the output is aligned. Make good on that!	2016-10-13 15:52:27 -07:00
Wesley W. Terpstra	84be93f9f3	axi4 Fragmenter: confirm correct handling of last	2016-10-13 14:01:23 -07:00
Wesley W. Terpstra	1c79a23a8b	axi4 Fragmenter: initialize error response to 0	2016-10-13 13:46:24 -07:00
Wesley W. Terpstra	958af132ba	axi4 Fragmenter: optimize dynamic slave lookup	2016-10-12 17:29:38 -07:00
Wesley W. Terpstra	11169d155c	axi4: add a Buffer to put between nodes	2016-10-12 17:08:52 -07:00
Wesley W. Terpstra	a9a3f7dd4e	tilelink2 RAMModel: include name of test in output	2016-10-12 17:08:52 -07:00
Wesley W. Terpstra	345eefd81b	axi4: include unit tests	2016-10-12 17:08:52 -07:00
Wesley W. Terpstra	a6c6d99848	axi4: prototype Fragmenter	2016-10-12 17:08:49 -07:00
Wesley W. Terpstra	c918aa6d89	axi4: name AdapterNode parameters properly	2016-10-12 17:02:02 -07:00
Wesley W. Terpstra	a423f97844	axi4: parameterized AXI master constraint for aligned access	2016-10-12 17:02:02 -07:00
Wesley W. Terpstra	673cf1fdb5	tilelink2 ToAXI4: must create irrevocable D for now	2016-10-12 17:02:01 -07:00
Wesley W. Terpstra	8e92ac32b7	tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom	2016-10-12 17:02:01 -07:00
Wesley W. Terpstra	38b6c1c820	tilelink2 axi4: RegisterRouter can cut ready dependency	2016-10-12 17:02:01 -07:00
Wesley W. Terpstra	dc26736f32	axi4 tilelink2: include minAlignment and maxAddress in slaves	2016-10-12 17:02:01 -07:00
Wesley W. Terpstra	538437384a	tilelink2 Fragmenter: combine AccessAck errors	2016-10-12 17:02:01 -07:00
Wesley W. Terpstra	4caa543ad7	tilelink2: Fragmenter should not cut Acquire parameters ... The correct response to misuse is to fail a requirement check. Pretending that things are not caches could lead to inconsistency.	2016-10-11 22:38:03 -07:00
Wesley W. Terpstra	6336f94fa2	tilelink2: only caches can support B requests	2016-10-11 22:38:02 -07:00
Wesley W. Terpstra	4a975ca380	tilelink2: add a rightOR to go with our leftOR	2016-10-11 22:38:02 -07:00
Wesley W. Terpstra	b2a5d18e37	diplomacy: simplify address range fragmentation	2016-10-11 22:36:21 -07:00
Wesley W. Terpstra	73e9508c09	Merge pull request #387 from ucb-bar/safer-crossings ... Safer crossings	2016-10-10 14:44:33 -07:00
Wesley W. Terpstra	b0e33f4a39	tilelink2: use TLArbiter in HintHandler	2016-10-10 13:15:28 -07:00
Wesley W. Terpstra	683a2e6785	tilelink2: refactor firstlast helper method	2016-10-10 13:15:28 -07:00
Wesley W. Terpstra	a404cd2abf	tilelink2: use NodeHandle to restore Crossing.node API	2016-10-10 13:15:28 -07:00
Wesley W. Terpstra	876609eb0e	diplomacy: add NodeHandles to support abstraction	2016-10-10 13:15:25 -07:00
Wesley W. Terpstra	97af07eb3e	tilelink2: clarify use of Isolation	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	76388117bb	regmapper: detect improper reset sequencing in RegisterCrossing	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	b5f5ef69c1	regmapper: eliminate race condition in RegisterCrossing bypass	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	f250426728	tilelink2: blow up if the channels carry data when they should not	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	1b09f1360d	AsyncQueue: adjust register names to match vals	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	e7f8a7e9ea	AsyncQueue: make it clear that the SyncChain is not Gray specific	2016-10-10 13:13:32 -07:00
Wesley W. Terpstra	52b8121e68	Apply "async_queue: Give names to all the registers which show up in the queue (#390)" ... Adjusted to include names for the new registers. Changes to RegisterCrossing were discarded.	2016-10-10 13:13:31 -07:00