Andrew Waterman
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6135615104
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unify cache backend interfaces; generify arbiter
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2012-02-20 00:51:48 -08:00 |
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Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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Christopher Celio
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1be9d15944
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Fixed bug regarding case sensitivity regarding ioICache,ioDCache
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2012-02-07 14:07:42 -08:00 |
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Henry Cook
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c5a4eaa0a1
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Associative cache, boots kernel
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2012-02-01 13:26:04 -08:00 |
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Andrew Waterman
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97c379f1d7
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made I$ associative
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2012-01-24 16:51:30 -08:00 |
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Andrew Waterman
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7f26fe2c44
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make icache size parameterizable
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2012-01-24 15:13:49 -08:00 |
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Andrew Waterman
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a5a020f97b
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update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
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Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
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2012-01-18 14:39:57 -08:00 |
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Andrew Waterman
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addfe55735
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add FPGA memory generator script
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2012-01-13 18:19:08 -08:00 |
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Andrew Waterman
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4807d7222b
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use replay to handle I$ misses
this eliminates a long path in the fetch stage
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2012-01-11 19:20:20 -08:00 |
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Andrew Waterman
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1a7bfd4350
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remove icache req_rdy signal
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2012-01-11 18:27:11 -08:00 |
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Andrew Waterman
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a8d0cd95e6
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hellacache now works
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2011-12-17 03:26:11 -08:00 |
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Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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218f63e66e
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code cleanup/parameterization
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2011-12-09 00:42:43 -08:00 |
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Rimas Avizienis
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fa784d1d7d
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made setReadLatency argument a parameter defined in consts.scala
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2011-12-05 00:33:17 -08:00 |
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Rimas Avizienis
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ff95cacb55
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icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
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2011-12-04 01:18:38 -08:00 |
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Rimas Avizienis
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e894b79870
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caches now use Mem4() memories for tag+data arrays
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2011-12-03 19:41:15 -08:00 |
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Rimas Avizienis
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c580180b66
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tweaks to cache/SRAM interface for TSMC65 SRAMs
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2011-12-02 02:01:08 -08:00 |
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Rimas Avizienis
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cf1965493b
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renamed SRAM modules to match TSMC65 MC generated SRAMs
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2011-12-01 13:14:33 -08:00 |
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Rimas Avizienis
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b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
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2011-11-14 04:13:13 -08:00 |
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Rimas Avizienis
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35af912bd2
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cache optimizations, cleanup, and testharness improvement
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2011-11-12 22:13:29 -08:00 |
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Rimas Avizienis
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83d90c4dab
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more itlb/dtlb/ptw fixes
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2011-11-12 15:00:45 -08:00 |
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Rimas Avizienis
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73416f224b
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more tlb/ptw debugging
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2011-11-12 00:25:06 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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9d63087eb2
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changed caches to use separate sram modules for tag and data arrays
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2011-11-07 00:58:25 -08:00 |
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Rimas Avizienis
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4d64099103
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cleanup
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2011-11-04 20:52:21 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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