8fc4d78c84
frontbus: provide fifofixer on the side of the front bus where masters connect
2017-09-05 15:03:38 -07:00
667d966410
TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming
2017-09-05 15:03:38 -07:00
94f06dc85c
pbus: turn down overkill buffering between PBus and SBus
2017-09-05 15:03:38 -07:00
c353f68dc0
buses: name dummy buffers too
2017-09-05 15:03:38 -07:00
3bde9506c6
coreplex: allow buffer chains on certain bus ports
2017-09-05 15:03:36 -07:00
57d0360c35
frontbus: Name the connection.
2017-08-30 18:07:34 -07:00
c99afe4c66
buses: Name all the things.
2017-08-30 17:31:42 -07:00
32cb358c81
coreplex: include optional tile name for downstream name stabilization
2017-08-30 15:48:55 -07:00
183fefb2b9
Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in
2017-08-30 15:27:56 -07:00
d5b62dffda
SystemBus: add stupidly many (4 more) buffers from sbus=>pbus
...
This should probably be reverted.
2017-08-30 14:22:49 -07:00
f7330028cc
Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter
2017-08-30 14:22:49 -07:00
173f185b17
Merge pull request #976 from freechipsproject/system-buffer
...
SystemBus: add output buffering
2017-08-30 23:22:13 +02:00
656609d610
SystemBus: split FIFOFixers along bus boundaries
...
If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
2017-08-30 13:28:11 -07:00
91c3fa2865
Merge pull request #979 from freechipsproject/buffer_params_debuginfo
...
TLBuffer: Add a nodedebugstring
2017-08-29 17:52:50 -07:00
a62ce0afe6
TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer.
2017-08-29 10:36:46 -07:00
bf19440db5
SystemBus: use a full buffer on slaves
2017-08-26 02:47:04 -07:00
bdaae40035
Merge pull request #973 from freechipsproject/named_buffers
...
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 16:31:14 -07:00
103b6bc6d3
systemBus: allowing naming the TLBuffers which get inserted
2017-08-24 14:49:12 -07:00
17134125e1
SystemBus: remove misnamed functions ( #972 )
...
These functions were actually for cross connecting chips.
2017-08-24 23:35:01 +02:00
6e689f55ed
Merge pull request #965 from freechipsproject/quash_x
...
async_reset_reg: Squash X's the same as for synchronous reg
2017-08-21 16:48:25 -07:00
81890e3a42
async_reg: Clean up some funky indentation
2017-08-21 16:06:36 -07:00
4f45379863
async_reset_reg: Squash X's the same as for reset reg
2017-08-21 14:33:19 -07:00
82df766f4a
Merge pull request #963 from freechipsproject/interrupt-order
...
Respect ISA requirements on interrupt priority order
2017-08-18 00:10:19 -07:00
8087a205cc
Remove redundant check in interrupt priority encoding
...
chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
cbe7c51b50
Respect ISA requirements on interrupt priority order
...
https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3
2017-08-17 21:27:08 -07:00
b1719cfee0
Fixing requirements for PAddrBits ( #961 )
...
Previously, the requirement for PAddrBits only checked to be equal or greater than the bundle bits. Changing it to check for these to match exactly as for cases when the PAddrBits greater than address bits we could run into scenarios which cause possible address wrap around issues.
2017-08-17 11:53:59 -07:00
1db4b3be9a
Merge pull request #957 from freechipsproject/param_jtag_vpi
...
jtag_vpi: Use Parameterized Black Box
2017-08-14 18:37:30 -07:00
8783d51c97
jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed
2017-08-14 17:25:47 -07:00
710a782145
HeterogenousBag: empty bags were being combined! ( #956 )
...
This lead to strange firrtl errors when you had two empty
HeterogeneousBags in the same Bundle.
2017-08-14 15:48:42 -07:00
e945f6e265
Merge pull request #955 from freechipsproject/fix-acquire-before-release
...
Fix acquire before release
2017-08-13 18:29:58 -07:00
57a5965bf4
Merge pull request #954 from freechipsproject/max-core-cycles
...
Add a +max-core-cycles PlusArg
2017-08-13 16:45:59 -07:00
88332bd885
max-core-cycles: Add a +max-core-cycles PlusArg
2017-08-13 15:47:14 -07:00
3cbc5262ec
Don't permit new acquires until the release queue is drained
...
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
...
oops...
2017-08-13 13:03:35 -07:00
41a2a03f90
Merge pull request #953 from freechipsproject/fix-dcache-ecc
...
Don't trigger ECC writebacks when a release is in flight
2017-08-12 16:47:19 -07:00
7387f2a93a
Don't block D-channel when handling a probe
...
This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
f191bb994c
PatternPusher: can now expect a certain output ( #952 )
2017-08-11 18:10:27 -07:00
baf769f924
tilelink: add PatternPusher, a device to inject a fixed traffic pattern ( #950 )
2017-08-11 15:07:10 -07:00
a3358f34a0
Fix priority inversion for two back-to-back divides ( #948 )
...
If the first one is killed for some unrelated reason (e.g. write port
hazard), the second one will still issue to the div-sqrt unit. While
it will itself later be killed, the fact that the later instruction
acquires a resource needed by the former instruction leads to deadlock.
2017-08-10 17:12:09 -07:00
fa867bc478
plusarg_reader: make synthesis path a no brainer ( #947 )
2017-08-10 16:35:30 -07:00
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
...
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
0b8b136831
Merge pull request #943 from freechipsproject/fix-ibuf
...
Fix IBuf bug
2017-08-09 10:38:35 -07:00
721770244e
Fix IBuf bug
...
Don't examine a packet's xcpt signal if it might be invalid. In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
fb2c22ca80
Merge pull request #944 from freechipsproject/fix-vlsi-mem-gen
...
memgen: also randomize ren and rand register
2017-08-08 23:18:08 -07:00
31b75987ca
Avoid width warning
2017-08-08 20:57:31 -07:00
8705b0e070
memgen: also randomize ren and rand register
2017-08-08 20:41:53 -07:00
97ad528a32
Merge pull request #941 from freechipsproject/bump-riscv-tools
...
Bump riscv-tools to bump riscv-tests for mi-csr test fix.
2017-08-08 18:50:29 -07:00
Henry Cook
Megan Wachs
Wesley W. Terpstra
Henry Styles
Andrew Waterman
Andrew Waterman
Shreesha Srinath
Yunsup Lee
Richard Xia