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Commit Graph

477 Commits

Author SHA1 Message Date
Andrew Waterman
890528c641 Avoid data corruption under correctable tag error during flush
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 16:09:44 -08:00
Andrew Waterman
34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)"
This reverts commit 44eb4d12b5.
2017-11-29 16:09:30 -08:00
Andrew Waterman
44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130)
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 09:42:00 -08:00
Andrew Waterman
5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127)
Firrtl can't DCE it because it would require analyzing the state machine.
2017-11-22 18:40:02 -06:00
Yunsup Lee
a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00
Andrew Waterman
5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db066303b.
2017-11-20 12:30:40 -08:00
Andrew Waterman
66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)"
This reverts commit 3db066303b.
2017-11-20 12:26:04 -08:00
Henry Cook
f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry Cook
b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115)
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
2017-11-17 17:26:48 -08:00
Wesley W. Terpstra
7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Henry Cook
7098ebf439
rocket: fix itim GetPropertyByHartId (#1109)
needs to use RocketTileParams.hartid instead of zipWithIndex
2017-11-13 19:25:20 -08:00
Andrew Waterman
4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend
Frontend improvements
2017-11-09 17:44:38 -08:00
Andrew Waterman
d0c6cbba6b Improve frontend branch prediction
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
2017-11-09 00:00:56 -08:00
Andrew Waterman
bb9d8264e2 "Correct" ITIM uncorrectable errors
This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors.  Previously, another core had to do it.
2017-11-08 22:15:03 -08:00
Andrew Waterman
5c1b34d854 Don't report a TL error if overwriting a whole ITIM word 2017-11-08 22:15:03 -08:00
Andrew Waterman
9b16d25861 Fix reporting of ITIM error addresses on slave-port accesses 2017-11-08 22:15:03 -08:00
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls (#1095)
Fragmenter: add a third case for earlyAck (PutFulls only)

It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).

Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
  If the PutFull was below the granularity, it was a single beat.
  If the PutFull was multi-beat, it exceeds the granularity.

Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
2017-11-08 15:31:19 -08:00
Andrew Waterman
34f38b0fb1 Don't permit vectoring of high interrupts
Send them to the base of the vector to obviate an adder
2017-11-07 01:59:30 -08:00
Andrew Waterman
6176b348dc Invalidate TL error bit in D$ once progress is made 2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts 2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187 Generate local interrupt #128 on bus errors
It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7 Make BusErrorUnit support 32-bit stores
Otherwise it isn't too useful for RV32!
2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt 2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1
Don't emit PTW covers when !usingVM
2017-11-06 18:03:36 -08:00
Andrew Waterman
95d00b13cc Report ITIM slave port errors to BusErrorUnit 2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6 Report ITIM uncorrectable errors over D-channel 2017-11-06 12:32:45 -08:00
Andrew Waterman
989eeb78f9 Prevent some unnecessary pipeline replays 2017-11-06 11:04:06 -08:00
Andrew Waterman
c8bc487ab8 Use pseudo-LRU policy in BTB
FIFO falls on its face if the working set doesn't fit in the BTB.
2017-11-03 16:27:04 -07:00
Andrew Waterman
f859da85ff Disable covers that don't apply to DTIM 2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee DTIM doesn't accept grants 2017-11-03 15:37:48 -07:00
Andrew Waterman
7bef935d2a
Don't emit PTW covers when !usingVM 2017-11-03 15:03:27 -07:00
Andrew Waterman
3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)
Workaround: disable interrupts and then do:

.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
2017-10-31 00:49:56 -07:00
Wesley W. Terpstra
a954f020a9 diplomacy: use new node style chaining 2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
9f83db998e tile: don't chain too many unneeded TileLink adapters (#1075) 2017-10-27 01:12:58 -07:00
Wesley W. Terpstra
c6f95570df IntNodes: moved from tilelink to their own package 2017-10-25 16:56:51 -07:00
Christopher Celio
c4978712c9 csr: allow for superscalar decode (#1069)
* CSR provides a decode port to check for an illegal instruction.
   * This commit now allows for multiple instructions in decode to get this
      illegal instruction information.
   * This commit leverages the existing decodeWidth parameter. This will
      potentially over-provision the number of decode ports needed for
      RVC-enabled cores.

Closes #1068
2017-10-25 13:58:26 -07:00
Andrew Waterman
21b5367259 Expand C.UNIMP correctly (#1052)
It was expanding to AMOADD.W, which is clearly not an illegal instruction.
2017-10-12 14:00:14 -07:00
Henry Cook
66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params
Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Henry Cook
1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b Conditionalize some covers that are sometimes impossible (#1043) 2017-10-10 17:14:33 -07:00
Henry Cook
9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Andrew Waterman
1474ab438d Remove extraneous signal 2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1 Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Andrew Waterman
986cbfb6b1 For Rockets without VM, widen vaddrBits to paddrBits
This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60 Don't route branch comparison result through ALU output mux
This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Wesley W. Terpstra
bd045a3b95 tilelink: split Acquire into Acquire{Block,Perm} (#1030)
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.

Instead of calling it Overwrite, we decided to split the Acquire type.

If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Henry Cook
45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
2017-10-05 00:26:44 -07:00
Andrew Waterman
7bcf28c585 Define fetchBytes in HasCoreParams, not Frontend
It is more generally useful.
2017-10-03 17:34:18 -07:00