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rocket-chip/src/main/scala/rocket
2017-10-09 18:33:50 -07:00
..
ALU.scala Don't route branch comparison result through ALU output mux 2017-10-07 17:36:24 -07:00
AMOALU.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Breakpoint.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
BTB.scala Fix BTB not being refilled on some indirect jumps 2017-07-26 02:13:43 -07:00
BusErrorUnit.scala diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Consts.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
CSR.scala Don't register interrupts in CSRFile 2017-10-03 17:34:18 -07:00
DCache.scala Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
Decode.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Events.scala Add method to print perf events 2017-07-25 15:19:16 -07:00
Frontend.scala Define fetchBytes in HasCoreParams, not Frontend 2017-10-03 17:34:18 -07:00
HellaCache.scala Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 2017-10-05 00:26:44 -07:00
HellaCacheArbiter.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
IBuf.scala Add instruction-trace port 2017-09-19 22:59:57 -07:00
ICache.scala Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
IDecode.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
Instructions.scala Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Multiplier.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
NBDcache.scala tilelink: split Acquire into Acquire{Block,Perm} (#1030) 2017-10-05 12:49:49 -07:00
package.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
PMP.scala Move microarchitecture-neutral params from Rocket to Core 2017-10-03 17:34:18 -07:00
PTW.scala Add some covers for L1 memory system 2017-10-09 18:33:36 -07:00
RocketCore.scala Don't route branch comparison result through ALU output mux 2017-10-07 17:36:24 -07:00
RVC.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
ScratchpadSlavePort.scala diplomacy: API beautification 2017-09-22 15:01:42 -07:00
SimpleHellaCacheIF.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00
TLB.scala Remove extraneous signal 2017-10-09 18:33:50 -07:00
TLBPermissions.scala Refactor package hierarchy and remove legacy bus protocol implementations (#845) 2017-07-07 10:48:16 -07:00