aad75f2285
Implement misa.C proposal
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This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
b487448961
Add FPUParams.fLen option, decoupled from xLen
2018-02-20 16:16:39 -08:00
efc6c9cbd3
Let user of CSRFile decide when to set tval
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I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
4bd9c477ea
Add cover properties for ECALL exceptions.
2017-11-30 14:27:04 -08:00
34f38b0fb1
Don't permit vectoring of high interrupts
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Send them to the base of the vector to obviate an adder
2017-11-07 01:59:30 -08:00
be3a3e0187
Generate local interrupt #128 on bus errors
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It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
c4978712c9
csr: allow for superscalar decode ( #1069 )
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* CSR provides a decode port to check for an illegal instruction.
* This commit now allows for multiple instructions in decode to get this
illegal instruction information.
* This commit leverages the existing decodeWidth parameter. This will
potentially over-provision the number of decode ports needed for
RVC-enabled cores.
Closes #1068
2017-10-25 13:58:26 -07:00
2786e42d99
Don't register interrupts in CSRFile
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They are usually registered outside the tile in a CDC.
2017-10-03 17:34:18 -07:00
5cfe070932
Add option to make misa read-only
2017-10-03 17:34:18 -07:00
09468a272b
Add option to remove basic counters (mcycle/minstret)
2017-10-03 17:34:18 -07:00
ab0821f25b
Move microarchitecture-neutral params from Rocket to Core
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This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
190d5c50d9
Remove deprecated custom-CSR support
2017-10-03 17:34:18 -07:00
78f3877e02
Trace tval field should be zero when not taking exceptions
2017-09-27 12:51:10 -07:00
583adeee88
Separate interrupt bit from cause field in trace bundle
2017-09-27 12:41:30 -07:00
026fa14bf8
Rename trace.addr -> iaddr
2017-09-20 14:32:41 -07:00
5b2f458214
Merge branch 'master' into ma-fetch
2017-09-20 12:18:03 -07:00
f5bd639863
Don't write badaddr on misaligned fetch exceptions
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It's optional, and we were doing it wrong before, so just don't do it.
2017-09-20 10:52:41 -07:00
4d6d6ff641
Add instruction-trace port
2017-09-19 22:59:57 -07:00
8087a205cc
Remove redundant check in interrupt priority encoding
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chooseInterrupts already sorts M interrupts above S interrupts.
2017-08-17 22:23:42 -07:00
cbe7c51b50
Respect ISA requirements on interrupt priority order
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a62e76cb16
2017-08-17 21:27:08 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
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* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
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This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
665c2a349c
Correct Debug + WFI Interactions
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1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
e3e77d68e6
PTW now does not require atomic memory operations, so take out the requirement ( #767 )
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Bug fix in CSR which manifest itself when compiling a config with no extension
2017-05-26 13:11:15 -07:00
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
7eefc12705
Support vectored stvec interrupts, too
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137812654e
2017-05-07 15:40:08 -07:00
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
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This reverts commit ea0714bfcb326bec83de
2017-05-07 15:23:21 -07:00
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
b9e042d2bf
Unconditionally write badaddr, possibly to zero
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59d33f6b83
2017-04-12 13:35:02 -07:00
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
a43bf2feae
Add vectored interrupt support
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4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
Andrew Waterman
Jacob Chang
Andrew Waterman
Richard Xia
Christopher Celio
Henry Cook
Megan Wachs