 Stephen Twigg
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3d35ccd401
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Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
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2015-02-03 18:10:54 -08:00 |
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Stephen Twigg
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e90f2484aa
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Sync with riscv-opcodes (csr register mapping)
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2014-04-08 15:48:37 -07:00 |
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Stephen Twigg
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6a02d15c21
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Merge branch 'master' into hwacha-port
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2014-02-04 17:05:03 -08:00 |
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Stephen Twigg
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3c3c469725
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Add exception signal to rocc interface
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2014-01-28 22:13:16 -08:00 |
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Stephen Twigg
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a662e85f2a
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Merge branch 'master' into hwacha
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2013-11-14 16:02:44 -08:00 |
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Stephen Twigg
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eae571e371
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Remove rocc memory simplifye module (Hwacha has its own)
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2013-11-05 15:31:03 -08:00 |
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Stephen Twigg
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36b85b8ee2
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Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
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2013-09-25 11:51:10 -07:00 |
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Stephen Twigg
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891e459625
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Export stats pcr register (#28 currently) to the top-level
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2013-09-25 01:16:32 -07:00 |
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Stephen Twigg
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730a6ec76b
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AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample
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2013-09-24 16:32:49 -07:00 |
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Stephen Twigg
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3532ae0b79
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
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2013-09-24 10:54:09 -07:00 |
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Stephen Twigg
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db1e09f0d0
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Fix issues with RoCC AccumulatorExample stalls on memory interface
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2013-09-23 00:21:43 -07:00 |
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Stephen Twigg
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158cee08af
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Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
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2013-09-22 03:18:06 -07:00 |
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Stephen Twigg
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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Stephen Twigg
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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Stephen Twigg
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
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