Wesley W. Terpstra
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54b73aef57
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tilelink2: WidthWidget and Fragmenter no longer erase latency
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2016-10-13 17:02:18 -07:00 |
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Wesley W. Terpstra
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200cf3dd13
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tilelink2 Nodes: include some options to test for conformance
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2016-10-13 17:02:18 -07:00 |
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Wesley W. Terpstra
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5d5b5a66f4
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tilelink2 RAMModel: fix a write-bad-data bug
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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e5a1483358
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tilelink2 Fragmenter: eliminate most of the registers on A
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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99c7003d11
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tilelink2: allow preemption of Fragmenter and WidthWidget
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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b42cfdc9dd
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tilelink2 Arbiter: there is only one winner
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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b6e9b0c558
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tilelink2 Arbiter: allow preemption of first beat
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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0aebf9e341
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tilelink2 ToAXI4: no arbitration path register needed
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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0e897b905f
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tilelink2 RegisterRouter: data path register is no longer required
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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c4eadd3ab3
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tilelink2 Monitor: enforce stricter transaction ordering
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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d8a1163131
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tilelink2 Monitor: don't enforce Irrevocable any more
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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405f66da32
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tilelink2 WidthWidget: cope with Decoupled inputs
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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e2e72ac979
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tilelink2 Fragmenter: cope with Decoupled input
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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023c6402e9
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tilelink2: switch to DecoupledIO syntax
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2016-10-13 17:02:17 -07:00 |
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Wesley W. Terpstra
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4c1c52486b
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axi4 Fragmenter: handle more inflight AXI requests than we have space
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2016-10-13 15:52:32 -07:00 |
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Wesley W. Terpstra
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8005266131
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axi4 Fragmenter: refine sideband FSM for case of last fragment
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2016-10-13 15:52:32 -07:00 |
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Wesley W. Terpstra
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19064e602b
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axi4 Fragmenter: align all output accesses
We promised the output is aligned. Make good on that!
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2016-10-13 15:52:27 -07:00 |
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Wesley W. Terpstra
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84be93f9f3
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axi4 Fragmenter: confirm correct handling of last
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2016-10-13 14:01:23 -07:00 |
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Wesley W. Terpstra
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1c79a23a8b
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axi4 Fragmenter: initialize error response to 0
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2016-10-13 13:46:24 -07:00 |
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Wesley W. Terpstra
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958af132ba
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axi4 Fragmenter: optimize dynamic slave lookup
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2016-10-12 17:29:38 -07:00 |
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Wesley W. Terpstra
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11169d155c
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axi4: add a Buffer to put between nodes
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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a9a3f7dd4e
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tilelink2 RAMModel: include name of test in output
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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345eefd81b
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axi4: include unit tests
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2016-10-12 17:08:52 -07:00 |
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Wesley W. Terpstra
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a6c6d99848
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axi4: prototype Fragmenter
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2016-10-12 17:08:49 -07:00 |
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Wesley W. Terpstra
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c918aa6d89
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axi4: name AdapterNode parameters properly
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2016-10-12 17:02:02 -07:00 |
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Wesley W. Terpstra
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a423f97844
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axi4: parameterized AXI master constraint for aligned access
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2016-10-12 17:02:02 -07:00 |
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Wesley W. Terpstra
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673cf1fdb5
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tilelink2 ToAXI4: must create irrevocable D for now
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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8e92ac32b7
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tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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38b6c1c820
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tilelink2 axi4: RegisterRouter can cut ready dependency
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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dc26736f32
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axi4 tilelink2: include minAlignment and maxAddress in slaves
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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538437384a
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tilelink2 Fragmenter: combine AccessAck errors
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2016-10-12 17:02:01 -07:00 |
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Wesley W. Terpstra
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4caa543ad7
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tilelink2: Fragmenter should not cut Acquire parameters
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
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2016-10-11 22:38:03 -07:00 |
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Wesley W. Terpstra
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6336f94fa2
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tilelink2: only caches can support B requests
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2016-10-11 22:38:02 -07:00 |
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Wesley W. Terpstra
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4a975ca380
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tilelink2: add a rightOR to go with our leftOR
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2016-10-11 22:38:02 -07:00 |
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Wesley W. Terpstra
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b0e33f4a39
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tilelink2: use TLArbiter in HintHandler
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2016-10-10 13:15:28 -07:00 |
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Wesley W. Terpstra
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683a2e6785
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tilelink2: refactor firstlast helper method
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2016-10-10 13:15:28 -07:00 |
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Wesley W. Terpstra
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a404cd2abf
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tilelink2: use NodeHandle to restore Crossing.node API
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2016-10-10 13:15:28 -07:00 |
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Wesley W. Terpstra
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876609eb0e
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diplomacy: add NodeHandles to support abstraction
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2016-10-10 13:15:25 -07:00 |
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Wesley W. Terpstra
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97af07eb3e
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tilelink2: clarify use of Isolation
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2016-10-10 13:13:32 -07:00 |
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Wesley W. Terpstra
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b5f5ef69c1
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regmapper: eliminate race condition in RegisterCrossing bypass
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2016-10-10 13:13:32 -07:00 |
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Wesley W. Terpstra
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f250426728
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tilelink2: blow up if the channels carry data when they should not
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2016-10-10 13:13:32 -07:00 |
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Wesley W. Terpstra
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6d6aa3eb13
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tilelink2: Isolation must also connect reset_n
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2016-10-10 13:13:31 -07:00 |
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Wesley W. Terpstra
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cb7b16f1a9
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util: exchange resets between AsyncQueue source and sink
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2016-10-10 13:13:31 -07:00 |
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Wesley W. Terpstra
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adf5f1807b
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tilelink2: ToAXI4 bridge added
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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e856cbe3a6
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axi4: SRAM for testing
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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abb02aa6f4
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axi4: add a RegisterRouter for generic devices
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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2f7081aeaf
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tilelink2: make mask generation reusable
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2016-10-10 11:21:50 -07:00 |
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Wesley W. Terpstra
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b29d34038e
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axi4: diplomacy capable AXI4
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2016-10-10 11:21:50 -07:00 |
|
Henry Cook
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1e69a2dc1c
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[tilelink2] allow TL monitors to be globally enabled or disabled (#392)
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2016-10-09 12:34:10 -07:00 |
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Wesley W. Terpstra
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e5ac0f717f
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tilelink2: split isolation gates by direction
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2016-10-07 12:03:43 -07:00 |
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