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Commit Graph

465 Commits

Author SHA1 Message Date
71bf929505 maskgen: support wider granularity result (#665)
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
051acee76c Debug: Fix off-by-1 for detecting nonexistent harts. 2017-04-07 16:47:16 -07:00
01372e1686 use Wire() correctly to assign a value 2017-04-07 16:47:16 -07:00
22c6f728c3 debug: Use flags for resume instead of program buffer. Untested. 2017-04-07 16:47:16 -07:00
d361e9e343 debug: temporarily leave preexec in place 2017-04-07 16:47:16 -07:00
0e2c34b0d6 debug: update register map with new spec 2017-04-07 16:47:16 -07:00
df5caba7bf debug: Make it easier to override parts of the Default Debug Config (#655)
* Handle single-step with a pipeline stall, not a flush

The pipeline flush approach broke when I changed the pipeline stage
the flush happens from

* debug: Make it easier to override parts of the Default Debug Config

* Fix typo in Debug code generation

abstractGeneratedI should be abstractGeneratedS when pulling out the opcode.
This doesn't actually break anything, but fix it for clarity.
2017-04-06 10:33:17 -07:00
2601740542 debug: fix some typos related to the ID->SEL mapping functions 2017-04-05 15:14:32 -07:00
b94f1f15b0 debug: redirect DMI NOPs to CONTROL register so things don't hang during reset 2017-04-05 15:14:32 -07:00
eef05cc1fc debug: Enforce mapping between hartsel and hartid, use more reasonable defaults for DATA and PROGBUF sizes. 2017-04-05 15:14:32 -07:00
629e9a2ef6 debug: Put DebugROM back inside the overall Debug Module (#647) 2017-04-03 16:36:53 -07:00
d2c1bdc2ce Debug Controls (#639)
* debug: Bump OpenOCD version to one that drives resets and sets cmderr appropriately.

* debug: Export the dmactive and ndreset signals to the top level and drive reset as intended in the TestHarness.
2017-04-03 13:31:35 -07:00
375a039279 debug: Use proper write-1-to-clear ABSTRACTCS.cmderr behavior (because fesvr code is using correct spec) 2017-03-28 21:14:22 -07:00
42ca597478 debug: Breaking change until FESVR is updated as well.
* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
2017-03-27 21:19:08 -07:00
43804726ac tilelink2: more helpful requirement message 2017-03-27 21:05:05 -07:00
0c3d85b52b debug: add generated ROM contents and register fields. 2017-03-27 21:01:36 -07:00
5b339b6bbd tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
11507ac7d6 TLROM: Use Resource as a parameter rather than assuming SimpleDevice.
This allows more flexibility e.g. considering the ROM as part of other
devices.
2017-03-26 20:58:14 -07:00
bf648514e3 TLROM: allow name and compatibility strings to be provided by subclasses. 2017-03-26 20:58:14 -07:00
f36b1766f8 TLROM: use the smallest ROM implementation that works
The contents everywhere else are still zero.
2017-03-24 20:40:28 -07:00
cf168e419b Support SFENCE.VMA rs1 argument
This one's a little invasive.  To flush a specific entry from the TLB, you
need to reuse its CAM port.  Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.

This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation).  It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
797c18b8db Make some requirement failures more verbose (#608)
* tilelink: verbose requires in xbar

* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
bd08f10816 tilelink2: make sink ids optional (#607)
* tilelink2: make sink ids optional

* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
76f083b469 FIFOFixer: Not all D-channel messages are A-channel responses 2017-03-21 14:17:38 -07:00
198afddb4b tilelink2: add the FIFOFixer 2017-03-21 11:16:51 -07:00
c33f31dd3c tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
930438adba tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
fd521c56a6 tilelink2: add client-side FIFO parameterization 2017-03-21 11:16:51 -07:00
4eef317e84 RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
431cb41e27 tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E 2017-03-20 14:49:22 -07:00
04892fea01 Monitor: support early ack 2017-03-20 14:49:19 -07:00
278f6fea24 tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
778e189bba Monitor: ProbeAckData and ReleaseData may carry an error 2017-03-20 11:44:13 -07:00
48c7aed4e1 Monitor: any probe supported by the client is legal 2017-03-20 11:34:19 -07:00
c9459fe4eb tilelink2 Xbar: don't use unnecessary ports 2017-03-19 17:02:24 -07:00
7971947d6c tilelink2 Monitor: don't inspect bits if valid is forbidden 2017-03-19 16:34:23 -07:00
a4ca424a22 AHBToTL: finally get the error signal right? (#594) 2017-03-18 22:24:20 -07:00
f6daa782d3 AHBToTL: fix the order of updates to d_pause (#592) 2017-03-17 19:34:40 -07:00
dcc9827ab4 Rename Prci.scala to Clint.scala (#591)
The internals of this were renamed to CoreplexLocalInterrupter, so changing the top level name to match.
2017-03-17 15:36:10 -07:00
db55a1d755 Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
9b5b3279a6 AHBToTL: don't report error during idle cycles 2017-03-16 18:18:29 -07:00
5efd38bf97 apb: put both aFlow options under regression 2017-03-16 15:36:14 -07:00
882a7ff8ff TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
e31b84af33 axi4: use common BufferParams 2017-03-16 15:32:17 -07:00
ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
963d244094 unittest: try both aFlow settings of TLToAHB 2017-03-16 15:13:57 -07:00
604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
c95c2ca9c8 AHB: include bridge unit tests 2017-03-14 18:34:21 -07:00