6d6fc38787
BusBlocker: lock bit should affect the prior PMP address, not next
2017-08-08 17:00:12 -07:00
809c7e8551
Don't merge stores that manifest WAW hazards
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The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
3ef6e4c9f2
Merge pull request #939 from freechipsproject/bus-blocker
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tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 15:06:55 -07:00
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
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Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
8f261adc6b
BusBlocker: change default policy to deny
2017-08-08 14:19:59 -07:00
0d76e96b88
tilelink: PMP controlled BusBlocker prevents bus accesses
2017-08-08 13:28:01 -07:00
7935c61c19
Don't report to the DTIM that data is cacheable
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Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
74d309c18e
Make I vs. D a static property of TLB, not an input pin
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The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
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The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
6d1d285464
Merge pull request #933 from freechipsproject/cinst
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Print out the compressed instruction when executing one
2017-08-07 21:40:10 -07:00
cc1e2af336
Merge pull request #934 from freechipsproject/critical-paths
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Revert "Remove one gate from D$ ECC check"
2017-08-07 19:41:08 -07:00
c8f8806df0
Merge pull request #932 from freechipsproject/tl-bus-delayer
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tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 19:01:39 -07:00
c4092dd0cc
tilelink: improve entropy of bus delayer
2017-08-07 17:36:07 -07:00
402907990c
Revert "Remove one gate from D$ ECC check"
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This reverts commit 7d94074b05
2017-08-07 17:33:20 -07:00
2910d6fa2a
tilelink: make bus xbar protected so it can be suggestNamed
2017-08-07 17:30:24 -07:00
fc0d5fcf98
Print out the compressed instruction when executing one
2017-08-07 17:21:53 -07:00
e27072e063
Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse
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Fix ram model source reuse
2017-08-07 16:56:13 -07:00
c457c9cb9f
tilelink: allow insertion of TLDelayer on TLBus outward node
2017-08-07 16:43:06 -07:00
f8b45564d1
tilelink: RAMModel must support source reuse
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If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
2017-08-07 16:01:15 -07:00
558fc7f293
maskrom: retain data for d channel is not ready
2017-08-07 12:17:10 -07:00
7fd8bb1159
Merge pull request #928 from freechipsproject/critical-paths
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Critical paths
2017-08-06 18:50:59 -07:00
658e36f98b
Reduce fanout on frontend io.cpu.req.valid signal
2017-08-06 17:38:51 -07:00
7d94074b05
Remove one gate from D$ ECC check
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The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
d03fdc4f30
diplomacy: seal the LazyModuleImpLike trait ( #927 )
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This makes sure that all the base classes call instantiate()
2017-08-06 17:32:23 -07:00
aa60c6944b
diplomacy: provide default clock/reset for LazyRawModuleImp
2017-08-06 13:40:07 -07:00
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
b9b4142bb4
Get s2_nack off the critical path
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We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively). This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
bc298bf146
Optimize ShiftQueue for late-arriving deq.ready
2017-08-04 22:06:37 -07:00
6112adfbb0
Get L2 TLB tag/parity check off the D$ arbitration path
2017-08-04 17:01:51 -07:00
8d97684555
Fix L2 TLB perfctr
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It was counting conflict misses but not cold misses.
2017-08-04 17:01:31 -07:00
df7f09b9ce
Get I$ ECC check further off critical path
2017-08-04 16:59:21 -07:00
4bfbe75d74
Avoid pipeline replays when fetch queue is full
2017-08-04 16:59:21 -07:00
a45997d03f
Separate I$ parity error from miss signal
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Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
2017-08-04 16:59:21 -07:00
06a831310b
Shave a gate delay off I$ backpressure path
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The deleted code was a holdover from Hwacha's vector fences.
2017-08-04 13:12:43 -07:00
ecc2ee366c
Shave a few gate delays off IBuf control logic
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It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
2017-08-04 13:12:43 -07:00
7937db0c84
Merge pull request #919 from freechipsproject/imiss-perf-counter
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Fix I$ miss perfctr
2017-08-04 01:04:23 -07:00
017ac130c1
Merge pull request #922 from freechipsproject/bigger_tl_xbar
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TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 16:52:56 -07:00
50c85f1b62
TLXbar: Allow more masters and slaves and issue a warning.
2017-08-03 15:46:06 -07:00
ba4eecc0f0
Use UIntToOH1 ( #921 )
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Closes #920
2017-08-03 14:55:39 -07:00
f483bab4aa
Fix I$ miss perfctr
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The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
1be1433f04
Merge pull request #918 from freechipsproject/icache-prefetch
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Icache prefetch
2017-08-02 21:22:20 -07:00
d66e8f8e80
Merge pull request #914 from freechipsproject/critical-paths
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Fix some critical paths
2017-08-02 19:05:31 -07:00
3fc7100048
Merge pull request #917 from freechipsproject/fuzzer_order
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TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 18:39:59 -07:00
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
744cdb2f72
Make TLB report when it's safe to prefetch within a page
2017-08-02 17:09:38 -07:00
595415d207
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
fc5c04ed4b
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
2017-08-02 14:44:18 -07:00
7d2dd3769f
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
