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riscv/rocket-chip
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d66e8f8e80eef30837876f19869d9c061015486e
rocket-chip/src/main/scala
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Andrew WatermanandGitHub d66e8f8e80 Merge pull request #914 from freechipsproject/critical-paths
Fix some critical paths
2017-08-02 19:05:31 -07:00
..
amba
tilelink: Error device supports Acquire
2017-07-27 18:32:58 -07:00
config
Refactor package hierarchy and remove legacy bus protocol implementations (#845)
2017-07-07 10:48:16 -07:00
coreplex
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
devices
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
diplomacy
diplomacy: Pretty Print for TransferSizes
2017-08-02 11:40:50 -07:00
groundtest
chiplink: adjust bus view to include the splitter (#886)
2017-07-24 21:41:17 -07:00
jtag
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
regmapper
add cloneType to RegisterWriteIO and RegisterReadIO (#874)
2017-07-18 18:52:31 -07:00
rocket
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
system
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
tile
Use 1-entry queue on processor-side E-channel
2017-07-31 18:06:54 -07:00
tilelink
TLFuzzer: Correct the number of ordered clients created
2017-08-02 15:48:21 -07:00
unittest
Combine Coreplex and System Module Hierarchies (#875)
2017-07-23 08:31:04 -07:00
util
tilelink: add mask rom
2017-07-31 21:34:04 -07:00
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