riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
2,985 Commits 1 Branch 0 Tags
64bde1060c444891b8068162d209a582dc831766
Commit Graph

1145 Commits

Author SHA1 Message Date
Andrew Waterman
64bde1060c [rocket] remove unused code in ibuf 2016-08-02 15:26:09 -07:00
Andrew Waterman
2ce702dc0a [rocket] fix PTW critical path 
Pipeline the killing of a D$ request following a PTW cache hit.
 2016-08-02 15:19:48 -07:00
Andrew Waterman
7e9d139e49 [rocket] remove rocket-specific require() from HasCoreParameters 2016-08-02 15:19:48 -07:00
Andrew Waterman
832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Andrew Waterman
a6e009d8de [rocket] Fix frontend mask when fetchWidth == 1 2016-07-31 15:21:17 -07:00
Andrew Waterman
c49dad2e9d Improve PTW QoR 2016-07-29 17:56:42 -07:00
Andrew Waterman
058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Andrew Waterman
c465120610 [rocket] use more standard pattern for computing integer min 2016-07-29 17:56:42 -07:00
Andrew Waterman
ffac86b041 [rocket] only write badaddr on certain exceptions 2016-07-29 17:56:42 -07:00
Andrew Waterman
0d3d9fca25 [rocket] Allow zapping of BTB entries 
This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
 2016-07-29 17:56:42 -07:00
Andrew Waterman
8e0392f24b [rocket] don't hard-code instruction width in BHT 2016-07-29 17:56:42 -07:00
Andrew Waterman
8a7fc75b53 fix metadata race in blocking L1 DCache 2016-07-28 17:54:28 -07:00
Howard Mao
bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao
dcfcac9530 fix LRSC issue (RocketChip issue #86) 
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
 2016-07-26 18:41:52 -07:00
Howard Mao
51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Colin Schmidt
a43ad522dc add clock override to tile constructor (#42) 
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
 2016-07-21 17:56:52 -07:00
Ben Keller
c069e66056 Modify the RoCC interface to include status in the command queue. (#41) 
This addresses a bug in which changes in mstatus could
propagate to RoCCs before their time. Existing RoCCs that use
the status port will need to be modified to match this change.

This addresses the first half of #40.
 2016-07-18 17:40:50 -07:00
Howard Mao
2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Howard Mao
40a146f625 HellaCacheArbiter passes through if n == 1 2016-07-18 17:01:29 -07:00
mwachs5
cff8de9814 Use new Mul/Div parameters vs UseFastMulDiv (#48) 
* Use new Mul/Div parameters vs UseFastMulDiv

* Rename MulDivUnroll to MulUnroll
 2016-07-15 15:41:20 -07:00
Andrew Waterman
7cf44f9b25 clean up WideCounter implementation 2016-07-15 00:51:01 -07:00
Andrew Waterman
d78f1aacd0 Clean up some zero-width wire cases using UInt.extract 2016-07-14 22:08:01 -07:00
Andrew Waterman
da512d4230 Explicitly discard BTB index LSBs 2016-07-14 17:10:27 -07:00
Andrew Waterman
e6aab368a4 Replace ICacheBufferWays parameter with I$ constructor argument 2016-07-14 12:38:54 -07:00
Andrew Waterman
3d0b92afd7 Misc code cleanup 2016-07-14 12:09:34 -07:00
Andrew Waterman
b8884e8143 Simplify frontend virtual address extension code 2016-07-14 12:05:09 -07:00
Andrew Waterman
1699622730 Don't speculatively refill I$ in uncacheable regions 2016-07-09 01:10:58 -07:00
Howard Mao
f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Andrew Waterman
3d8939d3c3 Set misa.base = 1 for RV32 2016-07-07 15:32:21 -07:00
Andrew Waterman
2455a806af Make WFI instruction respect mie CSR setting 2016-07-07 15:31:17 -07:00
Andrew Waterman
35a983275e Guarantee one-hotness of BTB entries 2016-07-06 15:58:01 -07:00
Andrew Waterman
c0e6ecebfc Fix BTB perf bug 
In rare cases, it would replace into a different row than it recorded.
 2016-07-06 03:16:05 -07:00
Andrew Waterman
f3e22984d5 Remove uarch counters 
These will be replaced with the indirect TDR scheme used by breakpoints.
 2016-07-06 01:41:41 -07:00
Andrew Waterman
25fdabdd59 Don't implicitly create Vecs, since they're heavyweight 2016-07-06 01:41:31 -07:00
Andrew Waterman
8bd7e3932b Implement priv-1.9 PTE scheme 2016-07-05 19:19:49 -07:00
Andrew Waterman
ebefe57036 simplify BTB fetchWidth=1 special case 2016-07-04 23:43:47 -07:00
Andrew Waterman
2d325df60c Improve PTW simulation performance 2016-07-02 14:34:18 -07:00
Andrew Waterman
5aa8ef1855 Remove invalidation support from BTB 
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
 2016-07-02 14:27:29 -07:00
Andrew Waterman
663002ec0c Improve TLB simulation performance 2016-07-02 14:26:05 -07:00
Howard Mao
a9e0a5e2df changes to imports after uncore refactor 2016-06-28 14:09:31 -07:00
Andrew Waterman
c10691b616 Don't take interrupts on instructions in branch shadow 
In situations like

       j 1f
       nop
    1: nop

the interrupt could be taken on the first nop.
 2016-06-28 12:47:49 -07:00
Andrew Waterman
a70dee17ea Make RoCC energy-saving logic mirror same for D$ 2016-06-28 12:47:45 -07:00
Andrew Waterman
6f85056494 Remove reliance on HtifKey 2016-06-23 13:18:51 -07:00
Andrew Waterman
6d43c0a945 Mask interrupts during single-step 2016-06-23 00:01:06 -07:00
Andrew Waterman
5644a2703a Avoid need for FENCE.I in debug programs 
This is a hack to work around caching the (uncacheable) debug RAM.  The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
 2016-06-23 00:01:06 -07:00
Andrew Waterman
7f88a00a38 Always verify BTB result; don't bother flushing it 
This improves CPI for things like

    lbu t0, (t0)
    j foo
    addi t0, t0, 1

where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
 2016-06-23 00:01:06 -07:00
Howard Mao
4c31248917 make sure UseAtomics is on when PTW is being used 2016-06-22 16:09:45 -07:00
Howard Mao
d1c83ccda0 change Tile interface to allow arbitrary number of cached and uncached channels 2016-06-20 09:55:30 -07:00
Andrew Waterman
60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Andrew Waterman
0b4c8e9af7 Add D-mode single-step support 2016-06-15 16:21:24 -07:00