Howard Mao
1c2bf6e938
make list of unit tests a a parameter
2016-07-18 09:33:16 -07:00
Howard Mao
69eebaf362
factor out unit tests into separate package
2016-07-18 09:33:16 -07:00
Matthew Naylor
4af6313288
TraceGen: Lookup -> MuxLookup
...
A recent commit to tracegen.scala introduced a call to BitPat() which
seems to mess up the subsequent call to Lookup(). (This function
seems undocumented so I'm not sure what's going on.) As a fix, I've
removed the call to BitPat() and replaced Lookup() with MuxLookup().
2016-07-17 22:28:18 +01:00
Howard Mao
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
Howard Mao
59d700bf66
fix combinational loop in NASTI -> HASTI converter
2016-07-15 18:45:37 -07:00
mwachs5
cff8de9814
Use new Mul/Div parameters vs UseFastMulDiv ( #48 )
...
* Use new Mul/Div parameters vs UseFastMulDiv
* Rename MulDivUnroll to MulUnroll
2016-07-15 15:41:20 -07:00
Megan Wachs
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
Howard Mao
897e6ccf8a
fix Hasti and Smi converters
2016-07-15 15:39:00 -07:00
Megan Wachs
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
Howard Mao
84098db81f
add a TileLinkTestRAM
2016-07-15 11:03:26 -07:00
Andrew Waterman
7cf44f9b25
clean up WideCounter implementation
2016-07-15 00:51:01 -07:00
Andrew Waterman
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
Andrew Waterman
d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
Andrew Waterman
da512d4230
Explicitly discard BTB index LSBs
2016-07-14 17:10:27 -07:00
Andrew Waterman
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
Andrew Waterman
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
Andrew Waterman
3d0b92afd7
Misc code cleanup
2016-07-14 12:09:34 -07:00
Andrew Waterman
b8884e8143
Simplify frontend virtual address extension code
2016-07-14 12:05:09 -07:00
Howard Mao
66b9c5ad05
fix up cloneType calls in clock crossers
2016-07-13 14:31:19 -07:00
Wesley W. Terpstra
eeae74e3fc
nasti: include convenient clock crossing helpers
2016-07-13 14:20:25 -07:00
Wesley W. Terpstra
c33c0944be
crossing: first clock crossing, the handshaker
2016-07-13 14:20:25 -07:00
Howard Mao
18ea58c85f
remove unnecessary CAMs from converters
2016-07-13 12:42:50 -07:00
Howard Mao
b122a54c32
don't allow more outer IDs than inner IDs
2016-07-13 12:42:28 -07:00
Howard Mao
37fd11870c
fix up ReorderQueue CAM
2016-07-13 12:11:43 -07:00
Howard Mao
de1e25f3d1
reduce usage of CAMs in converters
2016-07-13 11:20:50 -07:00
Howard Mao
c0dc09b3a1
don't use CAM in ReorderQueue if not necessary
2016-07-13 11:08:15 -07:00
Howard Mao
f3775df04d
fix the condition under which comparator error signal is set
2016-07-12 18:37:13 -07:00
Howard Mao
4c79215fde
add a script for checking comparator trace
2016-07-12 14:42:04 -07:00
Howard Mao
88dc0b983a
make sure Comparator logs correctly when prefetching off
2016-07-12 14:36:46 -07:00
Howard Mao
676a536706
fix bugs from adding ComparatorSource backpressure
2016-07-12 13:50:34 -07:00
Howard Mao
d435bb4185
reduce hardware usage of Comparator to allow it to synthesize
2016-07-12 10:54:18 -07:00
Palmer Dabbelt
2f70136f90
Fix the Nasti to Smi Converter for single-word Nasti busses
...
There's a register that tracks what word within a Nasti transaction a
Smi response cooresponds to, since Smi itself doesn't have any
multi-word stuff. This breaks the single-word Nasti to Smi converter
due to what's essentially a 0-width wire bug: it ends up doing something
like
word_offset_into_nasti := nasti_address(3, 3)
when "word_offset_into_nasti" should really be a 0-bit register, but due
to some log2Up block size calculation logic it's actually a 1-bit
register. Thus, this expression ends up grabbing a bit of the address,
which causes odd addresses to get buffered incorrectly.
My fix is to just special-case the "Nasti bus width is the same as Smi
bus width" case.
2016-07-12 09:31:21 -07:00
Howard Mao
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
Howard Mao
b64998ec05
make sure dramsim reads and writes occur in the order they are received
2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
Howard Mao
18967642de
export more detailed status data from GroundTest
2016-07-11 16:41:55 -07:00
Wesley W. Terpstra
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
Howard Mao
e194677087
fix comparator PutBlock data generation and debug output
2016-07-11 12:15:37 -07:00
mwachs5
36720d915a
Update README.md ( #161 )
...
Correct typo in heading
2016-07-11 00:34:13 -07:00
Andrew Waterman
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
Andrew Waterman
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
Howard Mao
5a3d6a1583
NastiTest should cycle through write ids
2016-07-08 17:55:02 -07:00
Howard Mao
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
Howard Mao
d80c2f480f
make NastiConverterTest act as generator and share blocks
2016-07-08 13:39:46 -07:00
Howard Mao
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
