Howard Mao
800e62412a
use the fast version of asm/bmark-tests
2016-06-24 15:36:10 -07:00
Howard Mao
d6ba0437ff
merge different configs into regression suites to reduce travis build times
2016-06-24 13:02:29 -07:00
Andrew Waterman
87a4858aa6
Exit from testbench, not C code
...
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
Howard Mao
4cd709c516
fix Comparator in groundtest
2016-06-23 15:47:24 -07:00
Howard Mao
238ce99f5c
fix requirement in Comparator
2016-06-23 15:47:09 -07:00
Andrew Waterman
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
Andrew Waterman
6fb07b1b79
Remove legacy HTIF things
2016-06-23 13:19:31 -07:00
Andrew Waterman
6f85056494
Remove reliance on HtifKey
2016-06-23 13:18:51 -07:00
Andrew Waterman
354b81c8fe
Remove legacy HTIF things
...
The SCR file is gone, too, because it is tightly coupled. The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
2016-06-23 13:17:11 -07:00
Andrew Waterman
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
Andrew Waterman
1844bac5bc
Use stop() to exit cleanly
2016-06-23 12:16:37 -07:00
Andrew Waterman
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
Andrew Waterman
f57524e0c1
Remove FENCE.I from debug ROM; specialize for RV64
2016-06-23 00:01:26 -07:00
Andrew Waterman
6d43c0a945
Mask interrupts during single-step
2016-06-23 00:01:06 -07:00
Andrew Waterman
5644a2703a
Avoid need for FENCE.I in debug programs
...
This is a hack to work around caching the (uncacheable) debug RAM. The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
2016-06-23 00:01:06 -07:00
Andrew Waterman
7f88a00a38
Always verify BTB result; don't bother flushing it
...
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
2016-06-23 00:01:06 -07:00
Howard Mao
255ef05e21
bump rocket
2016-06-22 17:59:05 -07:00
Howard Mao
338f959620
get rid of commented out code
2016-06-22 17:36:53 -07:00
Howard Mao
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
Howard Mao
4c31248917
make sure UseAtomics is on when PTW is being used
2016-06-22 16:09:45 -07:00
Howard Mao
5edb448a1f
get rid of slow DualCoreConfig in Travis for now
2016-06-22 16:09:14 -07:00
Howard Mao
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54
get rid of leftover backup memory code
2016-06-22 16:06:41 -07:00
Howard Mao
e3d3b2264a
fix MuxCase and MuxLookup
2016-06-21 14:03:10 -07:00
Howard Mao
0967f3cfed
use MuxCase and MuxLookup instead of MuxBundle
2016-06-21 14:01:23 -07:00
Howard Mao
e3391b36b2
get rid of MuxBundle now that MuxCase and MuxLookup are fixed
2016-06-21 10:43:44 -07:00
Howard Mao
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
Howard Mao
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
Howard Mao
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
Howard Mao
d1c83ccda0
change Tile interface to allow arbitrary number of cached and uncached channels
2016-06-20 09:55:30 -07:00
Andrew Waterman
4a8e6c773a
Fix +verbose flag for verilator
2016-06-17 21:09:08 -07:00
Andrew Waterman
60bddddfe6
Merge sptbr and sasid
2016-06-17 18:29:05 -07:00
Howard Mao
719fffff40
make sure updates from irel and iacq gated by tracker allocation
2016-06-17 17:15:02 -07:00
Howard Mao
b75b6fdcda
make sure no-data voluntary releases get tracked
2016-06-17 17:15:02 -07:00
Howard Mao
ebe95fa827
fix wmask buffer clearing in L2 agents
2016-06-16 15:34:31 -07:00
Howard Mao
aba13cee7f
fix BRAM slave so that it can correctly take all TileLink requests
2016-06-16 15:34:31 -07:00
Howard Mao
e716661637
make sure merged no-alloc put still allocs if original put allocs
2016-06-16 15:34:31 -07:00
Howard Mao
7e43b1d889
fix mistaken dequeueing from roq in TileLink unwrapper
2016-06-16 15:34:31 -07:00
Howard Mao
2789e60b6b
fix ignt_q logic
2016-06-16 15:18:58 -07:00
Henry Cook
16bfbda3c9
Refactor the TransactionTracker logic in all the L2 TileLink Managers.
...
They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
2016-06-16 15:18:48 -07:00
Howard Mao
181b11bf20
allow Comparator to disable prefetches (for testing BroadcastHub)
2016-06-16 15:14:02 -07:00
Howard Mao
a43a93b55c
add BRAMSlave unittest
2016-06-16 15:13:40 -07:00
Palmer Dabbelt
25ade44fe3
Don't build the Verilator man pages ( #141 )
...
These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
2016-06-16 10:13:21 -07:00
Colin Schmidt
ba35712f08
Merge pull request #140 from ucb-bar/verilator
...
Default to Chisel 3
2016-06-15 16:25:07 -07:00
Andrew Waterman
0b4c8e9af7
Add D-mode single-step support
2016-06-15 16:21:24 -07:00
mwachs5
2d2096e509
Add smaller ROM/RAM for 32-bit debug ( #60 )
2016-06-15 15:07:43 -07:00
Palmer Dabbelt
68ba33369b
Default to Chisel 3
...
Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
2016-06-15 14:01:43 -07:00
Palmer Dabbelt
e617bb8aa8
Start testing Chisel 3 in Travis
...
Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis. This disables Chisel 2 Travis tests because they're
too slow.
2016-06-15 14:01:22 -07:00
Palmer Dabbelt
f6432395cb
Allow the regressions to run more than once
2016-06-14 21:21:44 -07:00
Palmer Dabbelt
1525b4717e
Install Verilator when building the emulator
...
We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
2016-06-14 21:21:43 -07:00
