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Commit Graph

173 Commits

Author SHA1 Message Date
Adam Izraelevitz
548cf16061 Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse 2014-02-11 14:36:47 -08:00
Andrew Waterman
7c11cf49b8 Update riscv-tools 2014-01-21 16:23:32 -08:00
Andrew Waterman
b6c6bddb62 Add full CSRRx support and an asm test 2014-01-21 16:20:24 -08:00
Andrew Waterman
6f7ae01b1a More FPU fixes 2014-01-17 14:10:10 -08:00
Andrew Waterman
6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman
dfc13236d1 Linux works again! 2014-01-16 12:44:29 -08:00
Andrew Waterman
d99ee1f9c2 Update hardfloat, fixing SFMA unit 2013-12-09 20:31:58 -08:00
Andrew Waterman
ab6cd9c9e8 Update chisel, rocket 2013-12-09 15:09:48 -08:00
Andrew Waterman
a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Yunsup Lee
9e6e5adeba push uncore 2013-11-21 14:55:57 -08:00
Yunsup Lee
951226f413 fix slli/slliw encoding bug 2013-11-21 14:46:31 -08:00
Yunsup Lee
25fdf9827f push tests 2013-11-21 14:45:59 -08:00
Ben Keller
c137cf1a46 Added line to fix race condition in sbt compile; fixed .gitignores 2013-11-08 15:30:08 -08:00
Yunsup Lee
bb64c90092 forgot to put htif into uncore package 2013-11-07 15:42:21 -08:00
Yunsup Lee
1d6d4b4e96 move htif to uncore 2013-11-07 13:19:19 -08:00
Yunsup Lee
ad1d8f219e push riscv-tools 2013-11-05 21:10:49 -08:00
Yunsup Lee
04108270ff push riscv-tools 2013-10-29 22:54:00 -07:00
Andrew Waterman
a875233be6 update subrepos 2013-10-29 21:17:07 -07:00
Andrew Waterman
3c1d1f7981 Fix(?) SBT race by defining subproject build order 2013-10-29 13:27:36 -07:00
Andrew Waterman
8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
Andrew Waterman
c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
Stephen Twigg
437f7ed4af Push hardfloat (ignore target files) 2013-09-26 20:51:19 -07:00
Henry Cook
fc9c676fc1 add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
Stephen Twigg
f6d7e22c46 Push rocket (fix issue with uppermost bit of D$ req tag getting lost) 2013-09-25 11:52:01 -07:00
Stephen Twigg
36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Stephen Twigg
eb7e6f03b3 push rocket (AccumulatorExample fixes and documentation) 2013-09-24 16:33:32 -07:00
Stephen Twigg
472b947fbe push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory) 2013-09-24 16:16:12 -07:00
Stephen Twigg
eb03f61058 Properly ignore target files. Push uncore (properly ignore target files) 2013-09-24 16:03:28 -07:00
Stephen Twigg
081fcc4e63 push rocket (accelerator interface fixes) 2013-09-24 10:55:22 -07:00
Stephen Twigg
fba0ae0fec Push rocket 2013-09-23 00:26:27 -07:00
Stephen Twigg
324a6321bd Push tools (improve consistency: these tools will compile/test the new ISA encoding) 2013-09-22 03:24:11 -07:00
Stephen Twigg
2676ea8279 Push rocket (fix some issues with RoCC although some remain) 2013-09-22 03:19:43 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Huy Vo
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Andrew Waterman
42970c9a99 Update Rocket 2013-09-15 04:39:52 -07:00
Andrew Waterman
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Henry Cook
b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
Stephen Twigg
6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Stephen Twigg
f27c0fb010 Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2 2013-09-05 15:01:56 -07:00
Stephen Twigg
69daae0dae Add dependency resolvers to build.scala to fix build script 2013-09-05 14:56:41 -07:00
Yunsup Lee
2c47b4388a push rocket 2013-08-26 14:54:49 -07:00
Yunsup Lee
9003bc2614 push rocket 2013-08-24 22:42:57 -07:00
Yunsup Lee
d0674af13f forgot to push riscv-rocket 2013-08-24 22:15:38 -07:00
Yunsup Lee
ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee
76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee
694ebd65cf push uncore 2013-08-24 15:24:25 -07:00
Yunsup Lee
0884bc9789 fix DRAMSideLLCNull entries 2013-08-24 13:20:38 -07:00
Yunsup Lee
1e3ac0afa9 back to NTILES=1 2013-08-24 13:10:30 -07:00