riscv/rocket-chip
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215 Commits

Author SHA1 Message Date
Wesley W. Terpstra
b1cacc56ad SystemBus: restore correct order of FIFOFixer and Buffer 2017-09-05 16:41:39 -07:00
Wesley W. Terpstra
b74a419bfb FrontBus: FIFOFixer should not have a buffer between it and Xbar 2017-09-05 16:27:57 -07:00
Wesley W. Terpstra
e65f49b89a FrontBus: attach to splitter for cross-chip visibility 2017-09-05 15:03:41 -07:00
Wesley W. Terpstra
5886025b1a sbus => pbus: 2 buffers should already be enough 
There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.
 2017-09-05 15:03:38 -07:00
Henry Cook
a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry Cook
8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Megan Wachs
667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming 2017-09-05 15:03:38 -07:00
Megan Wachs
94f06dc85c pbus: turn down overkill buffering between PBus and SBus 2017-09-05 15:03:38 -07:00
Henry Cook
3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Megan Wachs
57d0360c35 frontbus: Name the connection. 2017-08-30 18:07:34 -07:00
Megan Wachs
c99afe4c66 buses: Name all the things. 2017-08-30 17:31:42 -07:00
Henry Cook
32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Megan Wachs
183fefb2b9 Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in 2017-08-30 15:27:56 -07:00
Wesley W. Terpstra
d5b62dffda SystemBus: add stupidly many (4 more) buffers from sbus=>pbus 
This should probably be reverted.
 2017-08-30 14:22:49 -07:00
Henry Styles
f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter 2017-08-30 14:22:49 -07:00
Wesley W. Terpstra
656609d610 SystemBus: split FIFOFixers along bus boundaries 
If you have a system with a lot of periphery slaves, you wan to FIFO fix
them on the periphery bus rather than paying the circuit cost at the sbus.
 2017-08-30 13:28:11 -07:00
Wesley W. Terpstra
bf19440db5 SystemBus: use a full buffer on slaves 2017-08-26 02:47:04 -07:00
Megan Wachs
103b6bc6d3 systemBus: allowing naming the TLBuffers which get inserted 2017-08-24 14:49:12 -07:00
Wesley W. Terpstra
17134125e1 SystemBus: remove misnamed functions (#972) 
These functions were actually for cross connecting chips.
 2017-08-24 23:35:01 +02:00
Henry Cook
2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Henry Cook
c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Yunsup Lee
6ef8ee5d4d tilelink: add mask rom 2017-07-31 21:34:04 -07:00
Wesley W. Terpstra
13d3ffbcaa tilelink: Filter now support arbitrary filter functions 2017-07-31 16:38:38 -07:00
Wesley W. Terpstra
540256e24a systembus: all slaves should have an output buffer 2017-07-29 00:13:33 -07:00
Wesley W. Terpstra
68064ba260 systembus: don't double down on buffers 
The order should be:
  master => buffer|xing => fifofixer => splitter => xbar
 2017-07-29 00:02:12 -07:00
Henry Cook
7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup 
Stabilize tile wrappers for downstream tools
 2017-07-28 10:52:59 -07:00
Wesley W. Terpstra
2e4f1611ed tilelink: Error device supports Acquire 
We need this if we want to divert traffic to it from a TL-C slave.
 2017-07-27 18:32:58 -07:00
Henry Cook
289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 2017-07-27 15:44:51 -07:00
Henry Cook
9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook
33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Yunsup Lee
6916e5cbfb coreplex: better names for RocketTiles in Verilog (#890) 2017-07-25 16:35:31 -07:00
Yunsup Lee
c9e467a668 coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887) 2017-07-25 00:55:55 -07:00
Wesley W. Terpstra
68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Yunsup Lee
dc435af30a fix HasRTCModuleImp (#885) 2017-07-24 20:24:59 -07:00
Henry Cook
01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Wesley W. Terpstra
4eface8a9e rocket: do not require FIFO order for memory-like regions 2017-07-12 17:39:00 -07:00
Henry Cook
4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Wesley W. Terpstra
bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Colin Schmidt
aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
 2017-06-22 12:07:09 -07:00
Wesley W. Terpstra
2f2fe0a973 clint: don't ask for what you know (nTiles) 2017-06-20 17:21:53 -07:00
Henry Cook
1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names 2017-06-20 17:18:45 -07:00
Henry Cook
5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Wesley W. Terpstra
1f8c4ba4ca CoreplexNetwork: don't force a buffer on the coherence manager 
Let the l2Config.coherenceManager create its own appropriate buffers.
This can matter if you need to make sure the buffer is in the right
place in the hierarchy for hierarchical place and route.
 2017-06-14 14:27:23 -07:00
Wesley W. Terpstra
b1917e7915 coreplex: add an ISPPort trait to add cross-connect points 2017-06-02 20:43:23 -07:00
Wesley W. Terpstra
81d372137a coreplex: unconditionally insert a Splitter between tiles and l1tol2 2017-06-02 20:43:21 -07:00
Wesley W. Terpstra
475ac93cdf coreplex: print memory map using DTS, also write a JSON for it 2017-06-02 14:27:40 -07:00
Wesley W. Terpstra
5994714970 diplomacy: move manager unification to meta-data only 
Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
 2017-06-01 15:30:20 -07:00
Yunsup Lee
6124bf0cc2 sort entires in the printed address map (#773) 2017-05-31 07:45:46 -10:00
Megan Wachs
d8996ea85f Empty commit to force travis 2017-05-16 22:56:58 -07:00
Henry Cook
5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00