Henry Styles f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter		2017-08-30 14:22:49 -07:00
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BaseCoreplex.scala	coreplex: change AsynchronousCrossing.sync default to 3	2017-07-27 15:44:51 -07:00
Configs.scala	tilelink: allow insertion of TLDelayer on TLBus outward node	2017-08-07 16:43:06 -07:00
FrontBus.scala	Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter	2017-08-30 14:22:49 -07:00
InterruptBus.scala	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
MemoryBus.scala	tilelink: make bus xbar protected so it can be suggestNamed	2017-08-07 17:30:24 -07:00
PeripheryBus.scala	tilelink: make bus xbar protected so it can be suggestNamed	2017-08-07 17:30:24 -07:00
Ports.scala	Combine Coreplex and System Module Hierarchies (#875)	2017-07-23 08:31:04 -07:00
ResetVector.scala	tilelink: add mask rom	2017-07-31 21:34:04 -07:00
RocketCoreplex.scala	Merge pull request #899 from freechipsproject/wrapper-dedup	2017-07-28 10:52:59 -07:00
RTC.scala	coreplex: retire RTCPeriod & introduce PeripheryBusParams.frequency (#887)	2017-07-25 00:55:55 -07:00
SystemBus.scala	SystemBus: split FIFOFixers along bus boundaries	2017-08-30 13:28:11 -07:00