riscv/rocket-chip
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637 Commits

Author SHA1 Message Date
Wesley W. Terpstra
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
Henry Cook
851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports 2016-09-15 14:25:47 -07:00
Henry Cook
245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
Henry Cook
a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor 2016-09-15 13:27:07 -07:00
Henry Cook
be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Henry Cook
c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00
Henry Cook
888f6a2a55 Revert "move UnitTest back into rocketchip module" 
This reverts commit f95b8c4ec2.
 2016-09-15 11:48:09 -07:00
Henry Cook
0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook
ab3814dcee Merge branch 'master' into tl2-irrevocable 2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Wesley W. Terpstra
1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881 [junctions] messed up the merge lulz 2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook
08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00
Andrew Waterman
5828e6042e Work around https://github.com/ucb-bar/firrtl/issues/299 2016-09-14 11:47:10 -07:00
Andrew Waterman
c3ddff809b Move PRCI from Coreplex to always-on block, where it belongs 2016-09-14 11:01:05 -07:00
Andrew Waterman
5566bf1b13 Don't route PLIC interrupts through PRCI 
The PLIC is local to the Coreplex, and PRCI should not be.
 2016-09-14 11:01:05 -07:00
mwachs5
47acbf928b Give AsyncCrossing slave interfaces registers visibility into when they were written (#288) 2016-09-14 00:17:26 -07:00
Howard Mao
bdb7b1de36 move tilelink-agnostic counters from uncore to util package 2016-09-13 20:47:05 -07:00
Howard Mao
1882241493 move junctions utils into top-level utils package 2016-09-13 20:47:04 -07:00
Henry Cook
7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d tilelink2: Unit Test for the RegisterCrossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
cc88bf1b08 junctions: give unit tests more time 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a tilelink2: unit test for the clock crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
c8e6d47884 tilelink2: add a clock crossing adapter 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
44501cdbf8 crossings: change defaults to sync=3 for safer settling time 
Make the matching AsyncQueue depth=8 to support full throughput
 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
3348236320 junctions: remove obsolete Handshaker crossing 2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
fe6a67dd0e tilelink2: add a RegisterCrossing primitive 2016-09-13 18:33:53 -07:00
Wesley W. Terpstra
d75f9d6a34 junctions: add an AsyncQueue 2016-09-13 17:38:18 -07:00
Wesley W. Terpstra
8142406d2e junctions: refactor the Crossing type 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
ecdfb528c5 crossing: refactor AsyncDecoupled to provide AsyncDecoupledCrossing with no clock domain 2016-09-13 15:51:18 -07:00
Wesley W. Terpstra
33a05786db tilelink2 RAMModel: fix put, get, putAck, getAck case (#282) 
This case should result in undefined data for the Get.
It was previously requiring the Get to return the new Put data,
which is only guaranteed by a FIFO device.
 2016-09-13 15:44:36 -07:00
Henry Cook
632b5896b9 Delete TestGraphs.scala 
Re-do later using Fuzzer
 2016-09-13 13:29:48 -07:00
Henry Cook
e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook
05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Andrew Waterman
61cbe6164d Add option to execute JAL from decode stage 
This is particularly helpful for designs that don't have a BTB, but
it becomes the critical path for designs with RVC.  Caveat emptor.
 2016-09-13 02:32:00 -07:00
Wesley W. Terpstra
606f19a17f tilelink2: RegisterRouter Unit Test 2016-09-12 22:13:39 -07:00
Wesley W. Terpstra
7005422651 tilelink2 HintHandler: don't HintAck in the middle of a multibeat op 2016-09-12 19:06:35 -07:00
Wesley W. Terpstra
273d3a73f2 tilelink2: Unit Test passes! 2016-09-12 18:39:50 -07:00
Wesley W. Terpstra
9874bc553a tilelink2: Fragmenter supports Hints 2016-09-12 17:31:59 -07:00
Wesley W. Terpstra
42955a0490 tilelink2: HintHandler optimize to nothing if unneeded 2016-09-12 17:31:16 -07:00
Wesley W. Terpstra
94761f714d tilelink2 HintHandler: fill in correct sink in responses 2016-09-12 17:26:40 -07:00
Wesley W. Terpstra
ca5f98f138 tilelink2: Hints are not special 
Hints have a TransferSize limit just like all other message types.
 2016-09-12 17:15:28 -07:00
Henry Cook
ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook
0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook
c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook
82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Henry Cook
a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook
0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Wesley W. Terpstra
7760459b76 tilelink2 RegisterRouter: add RegField test patterns 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
85ae77c108 tilelink2 RAMModule: carefully stage the pipeline to make BRAMs possible 2016-09-12 10:32:25 -07:00
Wesley W. Terpstra
9560df537c tilelink2 RegisterRouter: allow sub-4k devices in order to make useful unit tests 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
26f9e2dfbd tilelink2 Parameters: fix width=1 address truncation bug 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
98a4facac7 tilelink2 RAMModel: clear Mems on power-up 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
17f7ab18de tilelink2 RAMModel: model the state a RAM would have for Put+Gets 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
488b93d146 tilelink2 Parameters: if you support PutPartial, you must support PutFull 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
d6261e8ce8 tilelink2 Edge: add a numBeats1 method for predecremented code 2016-09-12 10:32:24 -07:00
Wesley W. Terpstra
5604049927 tilelink2 Buffer: support an unlimited number of channels 2016-09-12 10:32:24 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00