Merge branch 'master' into move-bootrom

src/main/scala/coreplex/UnitTest.scala

@@ -1,26 +0,0 @@
-package coreplex
-
-import Chisel._
-import unittest.UnitTestSuite
-import rocket.Tile
-import uncore.tilelink.TLId
-import cde.Parameters
-
-class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
-  require(tc.nSlaves == 0)
-  require(tc.nMemChannels == 0)
-
-  io.master.mmio.foreach { port =>
-    port.acquire.valid := Bool(false)
-    port.grant.ready := Bool(false)
-  }
-
-  io.debug.req.ready := Bool(false)
-  io.debug.resp.valid := Bool(false)
-
-  val l1params = p.alterPartial({ case TLId => "L1toL2" })
-  val tests = Module(new UnitTestSuite()(l1params))
-
-  override def hasSuccessFlag = true
-  io.success.get := tests.io.finished
-}

src/main/scala/junctions/crossing.scala

@@ -50,3 +50,44 @@ object AsyncDecoupledFrom
     AsyncDecoupledCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
   }
 }
+
+
+/**  Because Chisel/FIRRTL does not allow us
+  *  to directly assign clocks from Signals,
+  *  we need this black box module.
+  *  This may even be useful because some back-end
+  *  flows like to have this sort of transition
+  *  flagged with a special cell or module anyway.
+  */
+
+class SignalToClock extends BlackBox {
+  val io = new Bundle {
+    val signal_in = Bool(INPUT)
+    val clock_out = Clock(OUTPUT)
+  }
+
+  //  io.clock_out := io.signal_in
+}
+
+object SignalToClock {
+  def apply(signal: Bool): Clock = {
+    val s2c = Module(new SignalToClock)
+    s2c.io.signal_in := signal
+    s2c.io.clock_out
+  }
+}
+
+class ClockToSignal extends BlackBox {
+  val io = new Bundle {
+    val clock_in = Clock(INPUT)
+    val signal_out = Bool(OUTPUT)
+  }
+}
+
+object ClockToSignal {
+  def apply(clk: Clock): Bool = {
+    val c2s = Module(new ClockToSignal)
+    c2s.io.clock_in := clk
+    c2s.io.signal_out
+  }
+}

src/main/scala/rocketchip/TestConfigs.scala

@@ -7,7 +7,6 @@ import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
 import uncore.devices.NTiles
-import unittest._
 import junctions._
 import scala.collection.mutable.LinkedHashSet
 import scala.collection.immutable.HashMap
@@ -16,29 +15,6 @@ import scala.math.max
 import coreplex._
 import ConfigUtils._
 
-class WithUnitTest extends Config(
-  (pname, site, here) => pname match {
-    case BuildCoreplex => {
-      val groundtest = if (site(XLen) == 64)
-        DefaultTestSuites.groundtest64
-      else
-        DefaultTestSuites.groundtest32
-      TestGeneration.addSuite(groundtest("p"))
-      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
-      (p: Parameters, c: CoreplexConfig) => Module(new UnitTestCoreplex(p, c))
-    }
-    case UnitTests => (testParams: Parameters) =>
-      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", 0)
-    case FPUKey => None
-    case UseAtomics => false
-    case UseCompressed => false
-    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
-    case _ => throw new CDEMatchError
-  })
-
-class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
-
 class WithGroundTest extends Config(
   (pname, site, here) => pname match {
     case BuildCoreplex =>

src/main/scala/rocketchip/UnitTest.scala

@@ -0,0 +1,46 @@
+// See LICENSE for license details.
+
+package rocketchip.utest
+
+import scala.collection.mutable.LinkedHashSet
+
+import Chisel._
+import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
+import util.{ParameterizedBundle}
+import rocket._
+import uncore.tilelink._
+import uncore.tilelink2.{LazyModule, LazyModuleImp}
+import coreplex._
+import rocketchip._
+import unittest._
+
+class WithUnitTest extends Config(
+  (pname, site, here) => pname match {
+    case UnitTests => (testParams: Parameters) => {
+      val groundtest = if (site(XLen) == 64)
+        DefaultTestSuites.groundtest64
+      else
+        DefaultTestSuites.groundtest32
+      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
+    }
+    case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
+    case _ => throw new CDEMatchError
+  })
+
+class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
+
+class TestHarness(implicit val p: Parameters) extends Module {
+  val io = new Bundle {
+    val success = Bool(OUTPUT)
+  }
+
+  p(NCoreplexExtClients).assign(0)
+  p(ConfigString).assign("")
+
+  val l1params = p.alterPartial({ case TLId => "L1toL2" })
+  val tests = Module(new UnitTestSuite()(l1params))
+
+  io.success := tests.io.finished
+}

src/main/scala/uncore/tilelink2/RegisterCrossing.scala

@@ -4,6 +4,7 @@ package uncore.tilelink2
 
 import Chisel._
 import junctions._
+import uncore.util.{AsyncResetRegVec}
 
 // A very simple flow control state machine, run in the specified clock domain
 class BusyRegisterCrossing(clock: Clock, reset: Bool)
@@ -130,3 +131,56 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
   crossing.io.deq.ready := io.master_port.request.valid && !reg.io.busy
   crossing.io.enq.valid := Bool(true)
 }
+
+/** Wrapper to create an
+  *  asynchronously reset
+  *  slave register which
+  *  can be both read
+  *  and written using
+  *  crossing FIFOs.
+  */
+
+object AsyncRWSlaveRegField {
+
+  def apply(slave_clock: Clock,
+    slave_reset: Bool,
+    width:  Int,
+    init: Int,
+    master_allow: Bool = Bool(true),
+    slave_allow: Bool = Bool(true)
+  ): (UInt, RegField) = {
+
+    val async_slave_reg = Module(new AsyncResetRegVec(width, init))
+    async_slave_reg.reset := slave_reset
+    async_slave_reg.clock := slave_clock
+
+    val wr_crossing = Module (new RegisterWriteCrossing(UInt(width = width)))
+
+    val scope = Module (new AsyncScope())
+
+    wr_crossing.io.master_clock := scope.clock
+    wr_crossing.io.master_reset := scope.reset
+    wr_crossing.io.master_allow := master_allow
+    wr_crossing.io.slave_clock  := slave_clock
+    wr_crossing.io.slave_reset  := slave_reset
+    wr_crossing.io.slave_allow  := slave_allow
+
+    async_slave_reg.io.en := wr_crossing.io.slave_valid
+    async_slave_reg.io.d  := wr_crossing.io.slave_register
+
+    val rd_crossing = Module (new RegisterReadCrossing(UInt(width = width )))
+
+    rd_crossing.io.master_clock := scope.clock
+    rd_crossing.io.master_reset := scope.reset
+    rd_crossing.io.master_allow := master_allow
+    rd_crossing.io.slave_clock  := slave_clock
+    rd_crossing.io.slave_reset  := slave_reset
+    rd_crossing.io.slave_allow  := slave_allow
+
+    rd_crossing.io.slave_register := async_slave_reg.io.q
+
+    (async_slave_reg.io.q, RegField(width, rd_crossing.io.master_port, wr_crossing.io.master_port))
+
+  }
+
+}