617dd6fe1e
try travis suggestion on the jvm stages
2017-05-18 11:06:43 -07:00
93b2fa197e
Artefact output ( #545 )
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* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
3c1dac8c68
Match chisel3 userootunmanageddir - use RootProject/lib as unmanagedBase. ( #526 )
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This anticipates ucb-bar/chisel3#448 . When rocket-chip uses that version of chisel3, the extra copy to chisel3/lib may be removed.
2017-01-26 11:11:14 -08:00
e8e95d4bcf
regression: remove cde submodule update
2016-11-23 10:28:22 -08:00
f8bb67ab8f
Bind some Make vars early to avoid redundant evaluation
2016-10-28 11:56:13 -07:00
2b65478f3a
bump chisel/firrtl
2016-10-28 00:36:53 -07:00
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
97809b183f
refactor unittest framework
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as a result, there's another SUITE that needs to run
2016-09-14 18:10:21 -07:00
f7121a2a5b
support for BSD sed (GNU sed still works)
2016-09-14 12:21:39 -07:00
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
eba692786b
make sure FIRRTL jar gets updated timestamp
2016-08-19 13:45:23 -07:00
7b20609d4d
reorganize moving non-submodule packages into src/main/scala
2016-08-19 13:45:23 -07:00
ed827678ac
Write test harness in Chisel
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This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
a756856d84
make sure coreplex sources included in make dependencies
2016-08-11 14:27:03 -07:00
163cba6a85
make sure all regressions actually run
2016-08-10 14:52:06 -07:00
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
dab96096b4
Add firrtl build dependencies
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Without this when I update firrtl the new version doesn't get built, so
my build is constantly failing.
2016-08-05 14:45:00 -07:00
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
568bfa6c50
Purge legacy HTIF things
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The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
68ba33369b
Default to Chisel 3
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Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.
2016-06-15 14:01:43 -07:00
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
4afc9c69a0
streamline sbt
2016-04-19 14:22:22 -07:00
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
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This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
85cc632d5d
fix emulator debug build
2016-02-19 23:13:57 -08:00
95b065153d
Add CDE to the submodule list
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Without this I don't get rebuilds when toching a file in CDE.
2016-02-17 15:23:25 -08:00
db9de94588
Generate and use SCR address header files
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This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
1149a412cc
Support make-3.82 and newer
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make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests". This patch changes the hex file
rules to ensure they match between the two versions of make.
I've tried this with both make-3.81 and make-4.1, and they both work for me.
2016-01-28 12:19:11 -08:00
c5e9558571
Double Java MaxPermSize.
2015-12-07 12:05:06 -08:00
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
6f85ed191e
Add rocketchip_addons to the list of chisel srcs requiring rebuild
2015-09-16 12:28:03 -07:00
8e9c15c10d
If you don't have spike-disasm in your path, your path is dumped
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to stdout by this line every time you do anything in the entire repo.
2015-09-03 15:36:11 -07:00
333c594d2a
respect environment's CXX
2015-08-25 13:26:14 -07:00
34b9a7fdc5
Various Chisel3 compatibility changes
2015-08-03 18:54:56 -07:00
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
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Bump all submodules.
2015-07-29 18:15:45 -07:00
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
866396545d
For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten
2015-07-23 17:00:22 -07:00
caf89baeb7
update zscale
2015-07-23 13:59:45 -07:00
bd4ff35a4b
Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
2015-07-22 11:49:10 -07:00
d6df479870
move 'include /Makefrag' out of top-level Makefrag
2015-07-14 16:13:32 -07:00
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
09e29e8fe0
add zscale
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only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
