riscv/rocket-chip
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Author SHA1 Message Date
Henry CookandGitHub 71ddd797bf Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Henry CookandGitHub bab0b99d7a Merge pull request #1131 from freechipsproject/fix-dcache-tag-ecc-error-under-flush 
Avoid data corruption under correctable tag error during flush
 2017-11-30 12:27:15 -08:00
Henry CookandGitHub 9e0c26f855 Merge pull request #1118 from freechipsproject/basic-bus-blocker-3 
tile: bus blocker needs to know width
 2017-11-17 21:57:20 -08:00
Henry Cook f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry CookandGitHub b625e68360 tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Henry CookandGitHub 7098ebf439 rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Henry CookandGitHub d096fd206b coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Henry CookandWesley W. Terpstra b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry CookandWesley W. Terpstra 9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry CookandWesley W. Terpstra 95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Henry CookandGitHub 1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Henry Cook ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry CookandGitHub ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Henry Cook 66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry CookandGitHub b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Henry CookandGitHub 024ccd8ac2 Merge pull request #1048 from freechipsproject/local_int_hookup 
Correctly hook up the Local Interrupts into the Coreplex.
 2017-10-11 17:08:24 -07:00
Henry Cook 60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook 2dbe882e58 tilelink: add BasicBusBlocker device 2017-10-11 13:36:42 -07:00
Henry Cook 9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice 2017-10-11 12:45:36 -07:00
Henry Cook ec056535dc tilelink: add DeadlockDevice 2017-10-11 12:44:23 -07:00
Henry Cook 329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook 1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Henry CookandWesley W. Terpstra 75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Henry Cook 1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Henry Cook 37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook 660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Henry CookandGitHub 9040d921b5 Merge pull request #1031 from freechipsproject/non-contiguous-hartids 
Miscellaneous multicore cleanup
 2017-10-05 12:44:31 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Henry CookandGitHub 5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid 
Make use of the new DontTouch annotation
 2017-10-03 12:55:34 -07:00
Henry Cook d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Henry Cook cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire 
which contains hartid.
 2017-10-02 19:36:10 -07:00
Henry CookandGitHub 547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Henry CookandGitHub 33b46af806 Merge pull request #1007 from freechipsproject/tl-error 
Tl error
 2017-09-27 16:22:32 -07:00
Henry CookandGitHub 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry CookandGitHub 652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Henry CookandGitHub 5d08b37dab Merge pull request #1019 from freechipsproject/move-rocket-int-sync 
Move rocket output interrupt syncronizers
 2017-09-27 14:46:02 -07:00
Henry Cook f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Henry CookandGitHub 45d26ea130 Merge pull request #1015 from freechipsproject/coherence-manager 
coreplex: clean up coherence manager attachment point
 2017-09-26 11:09:48 -07:00
Henry Cook 9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
Henry CookandGitHub 5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire 
Halt and Catch Fire
 2017-09-22 09:30:30 -07:00
Henry Cook 81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook 28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Henry CookandGitHub 323a207bdd Merge pull request #1005 from freechipsproject/trace 
Rename trace.addr -> iaddr
 2017-09-20 15:34:45 -07:00
Henry CookandGitHub 1cb91eed41 Merge pull request #1003 from freechipsproject/ma-fetch 
Don't write badaddr on misaligned fetch exceptions
 2017-09-20 14:28:26 -07:00
Henry CookandGitHub 00cf089350 Merge pull request #1002 from freechipsproject/trace 
Add instruction-trace port
 2017-09-20 11:50:40 -07:00
Henry CookandGitHub 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Henry CookandGitHub 9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Henry CookandGitHub e8702e2687 Merge pull request #989 from freechipsproject/config-cleanups 
Clean up various Configs/Fields/Params
 2017-09-15 13:45:15 -07:00
Henry Cook e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook 56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook 37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry CookandGitHub 063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Henry Cook 9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook 3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Henry CookandWesley W. Terpstra a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Henry Cook 32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00
Henry CookandGitHub c8f8806df0 Merge pull request #932 from freechipsproject/tl-bus-delayer 
tilelink: allow insertion of TLDelayer on TLBus outward node
 2017-08-07 19:01:39 -07:00
Henry Cook c4092dd0cc tilelink: improve entropy of bus delayer 2017-08-07 17:36:07 -07:00
Henry Cook 2910d6fa2a tilelink: make bus xbar protected so it can be suggestNamed 2017-08-07 17:30:24 -07:00
Henry Cook c457c9cb9f tilelink: allow insertion of TLDelayer on TLBus outward node 2017-08-07 16:43:06 -07:00
Henry Cook 11332c1226 dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative 2017-07-31 14:03:30 -07:00
Henry CookandGitHub 7eeb9dfd88 Merge pull request #899 from freechipsproject/wrapper-dedup 
Stabilize tile wrappers for downstream tools
 2017-07-28 10:52:59 -07:00
Henry Cook b64b87ad07 tile: add option for tile boundary buffers 2017-07-27 17:30:51 -07:00
Henry Cook 289ef30dbc coreplex: change AsynchronousCrossing.sync default to 3 2017-07-27 15:44:51 -07:00
Henry Cook 266ed56e8d tile: turn off more slave port monitors 2017-07-27 15:28:53 -07:00
Henry Cook 9a483af6e8 coreplex: naming of tile wrappers 2017-07-27 15:16:48 -07:00
Henry Cook 33852ef965 coreplex: remove superfluous sink and source from wrapper 2017-07-27 14:23:03 -07:00
Henry CookandYunsup Lee 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Henry CookandGitHub 4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Henry CookandWesley W. Terpstra 6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Henry CookandWesley W. Terpstra ad4b454b49 isp: passthru based on edgesOut = edgesIn (#814) 2017-06-22 21:23:49 -07:00
Henry CookandGitHub 0fdaa28694 Merge pull request #811 from freechipsproject/isp-tweaks 
Assorted changes based on ISP use cases
 2017-06-20 19:24:28 -07:00
Henry Cook bf431c0a53 groundtest: fix test ram width 2017-06-20 18:11:22 -07:00
Henry Cook 1c97a2a94c allow re-positionable PLIC and Clint, and change coreplex internal network names 2017-06-20 17:18:45 -07:00
Henry Cook 5552f23294 tims: explictly name them for generated address map 2017-06-20 17:18:29 -07:00
Henry Cook 6b79842e66 dcache: just left shift by untagbits to get tag 
Always safe because of the requirement on coreplex/RocketTiles.scala:126
 2017-06-20 16:35:28 -07:00
Henry CookandGitHub 7521050a48 Merge pull request #810 from freechipsproject/isp-fixes 
ISP fixes
 2017-06-20 16:35:06 -07:00
Henry CookandGitHub 5368ea60fe Merge pull request #757 from freechipsproject/isp-port 
Inter-System-Port
 2017-06-15 13:07:19 -07:00
Henry CookandGitHub 8278d22fcd Merge pull request #776 from freechipsproject/lazy-raw-module-imp 
Use LazyMultiIOModuleImp to simplify top-level traits
 2017-06-13 15:50:12 -07:00
Henry Cook 80a3278139 travis: travis_wait to 80 2017-06-13 14:24:40 -07:00
Henry Cook 9bbde9767c rocketchip: top-level systems are now multi-IO modules 
Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
 2017-06-13 13:55:45 -07:00
Henry Cook 2e8a40a23f diplomacy: Allow LazyModuleImps to be based on RawModules or MultiIOModules 
And add a MonitorBase class to be connect's return type.
 2017-06-13 13:55:27 -07:00
Henry CookandGitHub 940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) 2017-05-22 19:37:11 -07:00
Henry CookandGitHub 991a67ac68 Merge pull request #749 from freechipsproject/unit-test-speedup 
Unit test speedup
 2017-05-17 16:28:42 -07:00
Henry CookandGitHub 733ebbce0e Update README.md (#748) 2017-05-17 14:53:56 -07:00
Henry CookandGitHub dfabf68d9c Merge pull request #746 from freechipsproject/fix-bundle-refs 
diplomacy: provide connect access to edges without bundles
 2017-05-17 12:28:46 -07:00
Henry Cook 5f22e91a7f rocc: fix RoccExampleConfig 2017-05-16 16:44:53 -07:00