riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,381 Commits 1 Branch 0 Tags 13 MiB
2587234838
Commit Graph

594 Commits

Author SHA1 Message Date
Wesley W. Terpstra
2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122 tilelink2 AddressDecoder: improved heuristic 2016-09-16 16:09:00 -07:00
Andrew Waterman
86b70c8c59 Rename PRCI to CoreplexLocalInterrupter 
That's all it's doing (there wasn't much PRC).
 2016-09-16 14:26:34 -07:00
Wesley W. Terpstra
4b1de82c1d RegField: separate UInt=>bytes and bytes=>regs 2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d tilelink2 RegField: .bytes should update more than one byte! 2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4 Fix deprecation warnings 2016-09-16 14:24:19 -07:00
mwachs5
a031686763 util: Do BlackBox Async Set/Reset Registers more properly (#305) 
* util: Do Set/Reset Async Registers more properly

The way BlackBox "init" registers were coded before was
not really kosher verilog for most synthesis tools.
Also, the enable logic wasn't really pushed down into the flop.

This change is more explicit about set/reset flops,
again this is only a 'temporary' problem that would go away
with parameterizable blackboxes (or general async reset support).

* Tabs, not spaces, in Makefiles

* util: Fix typos in Async BB Reg Comments
 2016-09-16 13:50:09 -07:00
Andrew Waterman
a94b4af92d Simplify AsyncResetRegVec and make AsyncResetReg companion object 2016-09-16 11:25:10 -07:00
Wesley W. Terpstra
dd19e0911e tilelink2: handle bus width=1 2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
e1d7f6d7df PRCI: always use bus width >= XLen 2016-09-15 22:15:07 -07:00
Wesley W. Terpstra
0e80f7fd0f HintHandler: don't violate Irrevocable rules 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072 testconfigs: disable atomics until AtomicAbsorber finished 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
38a9421c75 Comparator: don't compare addr_beat when it's irrelevant 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
669e3b0d96 Regression: fix-up address lookup 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956 RegisterRouter: compress register mapping for sparse devices 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc tilelink2: compute minimal decisive mask 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
fb24e847fd rocketchip: globals are for sissies 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
644f8fe974 rocketchip: switch to TL2 mmio + port PRCI 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3 tilelink2: make RegisterRouter constructor args public 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26 tilelink2: RegField splits up big registers 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
5c8e52ca32 devices: TL2 version of ROM 2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16 tilelink2: Legacy, manager_xact_id does not matter for uncached 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8 tilelink2: add an executable manager parameter 2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67 tilelink2: allow := on nodes outside the tilelink2 package 2016-09-15 21:28:55 -07:00
Jack Koenig
f2fe437fa4 Use CDEMatchError for improved performance (#304) 2016-09-15 19:47:18 -07:00
Henry Cook
0a65238920 Merge branch 'master' into tl2-irrevocable 2016-09-15 10:30:50 -07:00
Howard Mao
49863944c4 merge ClientTileLinkEnqueuer and ClientUncachedTileLinkEnqueuer objects into TileLinkEnqueuer 2016-09-14 21:36:27 -07:00
Howard Mao
f363f5f709 wrap TestHarness latency pipe in module 2016-09-14 21:16:54 -07:00
Howard Mao
f5db83a72f NTiles should not be a Knob 2016-09-14 21:16:54 -07:00
Howard Mao
646527c88e use named constants to set AXI resp, cache, and prot fields 2016-09-14 21:16:54 -07:00
Howard Mao
f95b8c4ec2 move UnitTest back into rocketchip module 2016-09-14 20:51:56 -07:00
Henry Cook
cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook
ab3814dcee Merge branch 'master' into tl2-irrevocable 2016-09-14 19:00:17 -07:00
Yunsup Lee
e404bea2ee Merge branch 'master' into move-bootrom 2016-09-14 18:58:48 -07:00
Wesley W. Terpstra
1c7d7f9d32 tilelink2 RegisterRouterTest: stall on both edges 2016-09-14 18:22:12 -07:00
Yunsup Lee
97809b183f refactor unittest framework 
as a result, there's another SUITE that needs to run
 2016-09-14 18:10:21 -07:00
Henry Cook
d35060b881 [junctions] messed up the merge lulz 2016-09-14 17:55:16 -07:00
Henry Cook
1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook
08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Megan Wachs
1308680f75 Add some async/clock utilities 2016-09-14 16:30:59 -07:00
Yunsup Lee
710f1ec020 Move BootROM from Coreplex to Periphery 2016-09-14 16:09:59 -07:00
Henry Cook
aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Andrew Waterman
565444c40e Make UnitTestCoreplex cope with an external MMIO network 2016-09-14 12:19:21 -07:00