Wesley W. Terpstra
02f89fb530
RegMapper: clarify interface is DecoupledIO
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
8a268268ad
tilelink2 RegField: clarify restrictions on functions
...
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
2016-10-02 02:24:02 -07:00
Wesley W. Terpstra
bff0ffa428
tilelink2 RegisterRouter: fix output data glitches
...
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
2016-10-02 02:24:02 -07:00
mwachs5
9a381e88d1
Suggest sane names for common objects ( #369 )
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* Suggest sane names for common objects frequently instantiated with factory methods
* Suggest names for common primitives using more Scala-esque Options
2016-09-30 16:19:25 -07:00
Wesley W. Terpstra
0ebab0976a
tilelink2 Isolation: add enable signal ( #368 )
2016-09-30 04:54:40 -07:00
Wesley W. Terpstra
d3547a6193
tilelink2: Isolation gate insertion module
2016-09-30 01:50:33 -07:00
Wesley W. Terpstra
9b0654be52
tilelink2 Crossing: helpful constructor objects
2016-09-30 01:48:47 -07:00
Wesley W. Terpstra
80f7bb49e3
tilelink2: helper objects operate on OutwardNodes
2016-09-30 01:39:35 -07:00
Wesley W. Terpstra
6d8c965f04
tilelink2 Crossing: cut the crossing between clock domains
2016-09-29 17:35:10 -07:00
Wesley W. Terpstra
20f42a8762
tilelink2: reuse the halves of the AsyncQueue
2016-09-29 17:35:08 -07:00
Wesley W. Terpstra
8e4c1e567c
tilelink2: add types for a TL clockless interface
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
02ce8c2ca4
tilelink2 Nodes: rename RootNode => BaseNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
754fcf9831
tilelink2: rename BaseNode to SimpleNode
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
cfdb8ca797
tilelink2 LazyModule: remove obsolete connect method
2016-09-29 17:33:11 -07:00
Wesley W. Terpstra
f2e438833c
tilelink2 Nodes: generalize a node into inner and outer halves
...
This lets us create nodes which transform from one bus to another.
2016-09-29 17:33:11 -07:00
Howard Mao
9910c69c67
Move a bunch more things into util package
...
A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were
* The AsyncQueue and AsyncDecoupledCrossing from junctions.
* All of the code in rocket's util.scala
* The BlackBox asynchronous reset registers from uncore.tilelink2
* The implicit definitions from uncore.util
2016-09-29 14:23:42 -07:00
Henry Cook
32f3f94882
[tilelink2] Fix zero-width wires in RAMModel.
2016-09-28 18:02:04 -07:00
Henry Cook
69e121260e
[tilelink2] Add unit tests for many TL2 components
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These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
2016-09-28 18:02:04 -07:00
Henry Cook
81123f84c9
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. ( #356 )
2016-09-27 18:06:21 -07:00
mwachs5
f9e0a7ac24
Merge branch 'master' into async_register_crossing
2016-09-27 15:54:34 -07:00
Wesley W. Terpstra
eaea138d0d
tilelink2: don't use chisel3 namespace ( #355 )
2016-09-27 14:44:26 -07:00
Henry Cook
f5502df6ab
Merge branch 'master' into async_register_crossing
2016-09-27 14:08:27 -07:00
Wesley W. Terpstra
357d06ac9c
tilelink2 WidthWidget: Gets must have their mask adjusted ( #353 )
...
The mask of a Get should also be converted.
This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
2016-09-27 14:06:02 -07:00
Megan Wachs
3ce08f40a5
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
2016-09-27 13:36:28 -07:00
Wesley W. Terpstra
d9e209365d
Tl2 addr width0 ( #346 )
...
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}
* tilelink2: use addr_lo instead of relying on truncation
Truncation can mess up if the width should be 0, but IS 1.
2016-09-26 17:00:03 -07:00
Wesley W. Terpstra
72c205b54f
tilelink2 AddressSet: add .misaligned(low, size) helper method ( #345 )
...
This helps devices with misaligned ranges still connect to TL2.
2016-09-26 16:01:09 -07:00
Wesley W. Terpstra
1773eb4405
tilelink2 LazyModule: output GraphML of the bus
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
35da9320bc
tilelink2 Nodes: expose connectivity in RootNode
2016-09-26 14:35:46 -07:00
Wesley W. Terpstra
d787bae0d0
tilelink2 Xbar: decouple ready from valid ( #338 )
...
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
2016-09-23 16:24:29 -07:00
Wesley W. Terpstra
47843d8ec1
tilelink2: maxLgSize should be accurate ( #332 )
2016-09-22 22:06:22 -07:00
Wesley W. Terpstra
c5706afc11
RegField: remove obsolete split method
...
This is now natively supported by the regmap(...) invocation.
2016-09-22 20:52:47 -07:00
Wesley W. Terpstra
fc44151f10
RegField: add name and description fields
...
In the future we can generate interesting documentation and headers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
5e34b313ee
RegMapper: regmap(...) now takes BYTE addresses
...
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.
This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
972ca06729
RegField: remove RegField.bytes; it was dangerous
...
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
2016-09-22 20:52:46 -07:00
Wesley W. Terpstra
a421469754
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
...
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.
For example, this:
peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
2016-09-22 20:52:46 -07:00
Henry Cook
391be8d740
tilelink2 RegisterRouter: minLatency is never more than 1
2016-09-22 15:51:15 -07:00
Wesley W. Terpstra
a3e88fa13a
tilelink2 Atomics: optimize the sign-extension circuit
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ed038678ef
tilelink2 Fuzzer: work around for firrtl/verilator performance issue
...
Big Vec()s cause very slow compilation.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
1e7480b6fc
tilelink2 Monitor: work around for firrtl/verilator performance issue
...
Big Vec()s cause problems for these tools.
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
ec2030df31
tilelink2 Legacy: convert TL1 atomic operand size
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e5da3eb8bb
tilelink2 Atomics: support arithmetic atomics
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
5b80fe5b51
tilelink2 Atomics: support Logical AMOs
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
4066fbe18f
tilelink2 RAMModel: exploit latency to remove bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
e0ade8c5a9
tilelink2 Atomics: exploit minLatency to eliminate bypass
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
3bb2580223
tilelink2 Monitor: detect minLatency violations
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
2b24c4b1b4
tilelink2: most adapters can wipe away latency
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
c115913624
tilelink2 Buffer: increase the minLatency on ports
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
05beb20dc4
tilelink2: specify the minLatency for SRAM+RR
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
44277c1db3
tilelink2 Parameters: include a minLatency parameter for optimization
2016-09-22 15:18:54 -07:00
Wesley W. Terpstra
cf39c32b0e
tilelink2 Fuzzer: test Atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
2b9403633d
tilelink2 RAMModel: support (by ignoring) atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
ce204f604a
tilelink2 AtomicAutomata: prototype flow control complete
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
42b10356fa
tilelink2: add a general-purpose Arbiter
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
7636e772c8
tilelink2 Fuzzer: only generate legal atomics
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
f5d604d8f8
tilelink2 Parameters: poison ports with unsafe atomics
...
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
2016-09-22 15:18:53 -07:00
Wesley W. Terpstra
d1151e2f0f
tilelink2 Nodes: split connect into eager and lazy halves
2016-09-22 15:18:50 -07:00
Wesley W. Terpstra
684072023f
tilelink2 Monitor: make it a LazyModule in the hierarchy
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
def497861b
tilelink2 Bundles: add 1-way snoop bundles
2016-09-22 15:14:20 -07:00
Wesley W. Terpstra
69a1f8cd1f
tilelink2 Monitor: detect if sources are mishandled
2016-09-22 15:14:19 -07:00
Albert Ou
d76b762657
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
...
This fixes an issue where passing addr_lo through unchanged triggered
unaligned address assertions in the Monitor.
2016-09-22 12:36:28 -07:00
Howard Mao
cd96a66ba6
replace verilog clock divider with one written in Chisel
2016-09-22 11:32:29 -07:00
Henry Cook
335e866176
[unittest] Parallelize UnitTestSuite ( #319 )
...
* [unittest] Parallelize UnitTestSuite so all tests have their own timer, runs until all finish or any timeout. Adds SimpleTimer.
* [util] Timer spacing cleanup
* [unittest] Remove Config reference to UnitTestTimeout
2016-09-21 13:05:22 -07:00
Wesley W. Terpstra
9817a00ed9
tilelink2: Fuzzer should check address validity before injection
2016-09-17 17:07:21 -07:00
Wesley W. Terpstra
b11839f5a1
tilelink2: differentiate fast/safe address lookup cases
2016-09-17 17:04:18 -07:00
Wesley W. Terpstra
b4baae4214
tilelink2: minimize Xbar decode logic
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
76d8ed6a69
tilelink2: remove 'strided'; !contiguous is clearer
2016-09-17 16:14:25 -07:00
Wesley W. Terpstra
fa0f119f3c
tilelink2: consider the implications of negative address mask
2016-09-17 16:14:22 -07:00
Wesley W. Terpstra
e437508548
tilelink2: track interrupt connectivity like in TL2
2016-09-17 14:43:48 -07:00
Wesley W. Terpstra
6c3269a1d8
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
Wesley W. Terpstra
a357c1d42e
tilelink2: create DTS for devices automagically
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
2587234838
tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
915a929af1
tilelink2: Nodes can now mix context into parameters
2016-09-16 17:28:47 -07:00
Wesley W. Terpstra
dae0918c85
tilelink2 RegisterRouter: support undefZero
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
f0f553f227
tilelink2 RegisterRouterTest: work around firrtl warning
...
Using io.wready leads to verilog that reads from the output...
Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
Port "io_wready" declared as output in module "RRTestCombinational_29" may
need to be inout. Coercing to inout.
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
3fcc1a4460
tilelink2 RegisterRouterTest: don't couple fire into helpers
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
2210e71f42
tilelink2 AddressDecoder: validate output of optimization
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
023a54f122
tilelink2 AddressDecoder: improved heuristic
2016-09-16 16:09:00 -07:00
Wesley W. Terpstra
4b1de82c1d
RegField: separate UInt=>bytes and bytes=>regs
2016-09-16 14:24:28 -07:00
Wesley W. Terpstra
943c36954d
tilelink2 RegField: .bytes should update more than one byte!
2016-09-16 14:24:24 -07:00
Andrew Waterman
6134384da4
Fix deprecation warnings
2016-09-16 14:24:19 -07:00
Wesley W. Terpstra
dd19e0911e
tilelink2: handle bus width=1
2016-09-15 22:15:11 -07:00
Wesley W. Terpstra
0e80f7fd0f
HintHandler: don't violate Irrevocable rules
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
f05222a072
testconfigs: disable atomics until AtomicAbsorber finished
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
30fa4ea956
RegisterRouter: compress register mapping for sparse devices
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
6b1c57aedc
tilelink2: compute minimal decisive mask
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
91e7da4de3
tilelink2: make RegisterRouter constructor args public
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3875e11b26
tilelink2: RegField splits up big registers
2016-09-15 21:28:56 -07:00
Wesley W. Terpstra
3f30e11f16
tilelink2: Legacy, manager_xact_id does not matter for uncached
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
ddd93871d8
tilelink2: add an executable manager parameter
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
9442958d67
tilelink2: allow := on nodes outside the tilelink2 package
2016-09-15 21:28:55 -07:00
Wesley W. Terpstra
1c7d7f9d32
tilelink2 RegisterRouterTest: stall on both edges
2016-09-14 18:22:12 -07:00
Henry Cook
1b53e477fa
Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
2016-09-14 17:50:17 -07:00
Henry Cook
e02d149cbe
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
2016-09-14 17:43:07 -07:00
Megan Wachs
1308680f75
Add some async/clock utilities
2016-09-14 16:30:59 -07:00
Henry Cook
aa3fa90fe3
[tilelink2] Monitor: miscopied name in assert message
2016-09-14 14:56:50 -07:00
Henry Cook
d76e19a6ab
[tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both?
2016-09-14 14:23:23 -07:00
mwachs5
47acbf928b
Give AsyncCrossing slave interfaces registers visibility into when they were written ( #288 )
2016-09-14 00:17:26 -07:00
Henry Cook
7dd4492abb
First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes.
2016-09-13 20:30:14 -07:00
Wesley W. Terpstra
d23ab7370d
tilelink2: Unit Test for the RegisterCrossing
2016-09-13 18:33:56 -07:00
Wesley W. Terpstra
acedd3688a
tilelink2: unit test for the clock crossing
2016-09-13 18:33:56 -07:00