Wesley W. Terpstra 4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass

2016-09-22 15:18:54 -07:00

..

AddressDecoder.scala

tilelink2 AddressDecoder: validate output of optimization

2016-09-16 16:09:00 -07:00

Arbiter.scala

tilelink2: add a general-purpose Arbiter

2016-09-22 15:18:53 -07:00

AtomicAutomata.scala

tilelink2 Atomics: exploit minLatency to eliminate bypass

2016-09-22 15:18:54 -07:00

Buffer.scala

tilelink2 Buffer: increase the minLatency on ports

2016-09-22 15:18:54 -07:00

Bundles.scala

tilelink2 Bundles: add 1-way snoop bundles

2016-09-22 15:14:20 -07:00

Crossing.scala

[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.

2016-09-14 17:43:07 -07:00

Edges.scala

tilelink2: differentiate fast/safe address lookup cases

2016-09-17 17:04:18 -07:00

Example.scala

Merge remote-tracking branch 'origin/master' into black_box_regs

2016-09-09 13:12:52 -07:00

Fragmenter.scala

tilelink2: most adapters can wipe away latency

2016-09-22 15:18:54 -07:00

Fuzzer.scala

tilelink2 Fuzzer: test Atomics

2016-09-22 15:18:53 -07:00

HintHandler.scala

tilelink2: most adapters can wipe away latency

2016-09-22 15:18:54 -07:00

IntNodes.scala

tilelink2 Nodes: split connect into eager and lazy halves

2016-09-22 15:18:50 -07:00

LazyModule.scala

tilelink2: get rid of fragile implicit lazyModule pattern, and support :=

2016-09-08 23:06:59 -07:00

Legacy.scala

testconfigs: disable atomics until AtomicAbsorber finished

2016-09-15 21:28:56 -07:00

Monitor.scala

tilelink2 Monitor: detect minLatency violations

2016-09-22 15:18:54 -07:00

Nodes.scala

tilelink2 Nodes: split connect into eager and lazy halves

2016-09-22 15:18:50 -07:00

package.scala

tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec

2016-09-08 21:34:20 -07:00

Parameters.scala

tilelink2 Parameters: include a minLatency parameter for optimization

2016-09-22 15:18:54 -07:00

RAMModel.scala

tilelink2 RAMModel: exploit latency to remove bypass

2016-09-22 15:18:54 -07:00

RegField.scala

RegField: separate UInt=>bytes and bytes=>regs

2016-09-16 14:24:28 -07:00

RegisterCrossing.scala

Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable

2016-09-14 17:50:17 -07:00

RegisterRouter.scala

tilelink2: specify the minLatency for SRAM+RR

2016-09-22 15:18:54 -07:00

RegisterRouterTest.scala

tilelink2: specify the minLatency for SRAM+RR

2016-09-22 15:18:54 -07:00

RegMapper.scala

tilelink2: specify the minLatency for SRAM+RR

2016-09-22 15:18:54 -07:00

SRAM.scala

tilelink2: specify the minLatency for SRAM+RR

2016-09-22 15:18:54 -07:00

TLNodes.scala

tilelink2 Parameters: include a minLatency parameter for optimization

2016-09-22 15:18:54 -07:00

WidthWidget.scala

tilelink2: most adapters can wipe away latency

2016-09-22 15:18:54 -07:00

Xbar.scala

tilelink2 Parameters: include a minLatency parameter for optimization

2016-09-22 15:18:54 -07:00