.. |
AddressDecoder.scala
|
tilelink2 AddressDecoder: validate output of optimization
|
2016-09-16 16:09:00 -07:00 |
Arbiter.scala
|
tilelink2 Xbar: decouple ready from valid (#338)
|
2016-09-23 16:24:29 -07:00 |
AtomicAutomata.scala
|
tilelink2 Atomics: optimize the sign-extension circuit
|
2016-09-22 15:18:54 -07:00 |
Buffer.scala
|
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
|
2016-09-22 20:52:46 -07:00 |
Bundles.scala
|
tilelink2: don't use chisel3 namespace (#355)
|
2016-09-27 14:44:26 -07:00 |
Crossing.scala
|
[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
|
2016-09-14 17:43:07 -07:00 |
Edges.scala
|
Tl2 addr width0 (#346)
|
2016-09-26 17:00:03 -07:00 |
Example.scala
|
RegMapper: regmap(...) now takes BYTE addresses
|
2016-09-22 20:52:46 -07:00 |
Fragmenter.scala
|
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
|
2016-09-22 20:52:46 -07:00 |
Fuzzer.scala
|
tilelink2: don't use chisel3 namespace (#355)
|
2016-09-27 14:44:26 -07:00 |
HintHandler.scala
|
tilelink2: change adapters to use TLAdapter(params, defaults)(node)
|
2016-09-22 20:52:46 -07:00 |
IntNodes.scala
|
tilelink2 Nodes: split connect into eager and lazy halves
|
2016-09-22 15:18:50 -07:00 |
LazyModule.scala
|
tilelink2 LazyModule: output GraphML of the bus
|
2016-09-26 14:35:46 -07:00 |
Legacy.scala
|
tilelink2 Legacy: convert TL1 atomic operand size
|
2016-09-22 15:18:54 -07:00 |
Monitor.scala
|
tilelink2 Monitor: work around for firrtl/verilator performance issue
|
2016-09-22 15:18:54 -07:00 |
Nodes.scala
|
tilelink2 Nodes: expose connectivity in RootNode
|
2016-09-26 14:35:46 -07:00 |
package.scala
|
tilelink2 Atomics: optimize the sign-extension circuit
|
2016-09-22 15:18:54 -07:00 |
Parameters.scala
|
tilelink2 AddressSet: add .misaligned(low, size) helper method (#345)
|
2016-09-26 16:01:09 -07:00 |
RAMModel.scala
|
tilelink2: don't use chisel3 namespace (#355)
|
2016-09-27 14:44:26 -07:00 |
RegField.scala
|
RegField: remove obsolete split method
|
2016-09-22 20:52:47 -07:00 |
RegisterCrossing.scala
|
crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
|
2016-09-27 13:36:28 -07:00 |
RegisterRouter.scala
|
tilelink2 RegisterRouter: minLatency is never more than 1
|
2016-09-22 15:51:15 -07:00 |
RegisterRouterTest.scala
|
[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356)
|
2016-09-27 18:06:21 -07:00 |
RegMapper.scala
|
tilelink2: don't use chisel3 namespace (#355)
|
2016-09-27 14:44:26 -07:00 |
SRAM.scala
|
tilelink2: specify the minLatency for SRAM+RR
|
2016-09-22 15:18:54 -07:00 |
TLNodes.scala
|
tilelink2 Parameters: include a minLatency parameter for optimization
|
2016-09-22 15:18:54 -07:00 |
WidthWidget.scala
|
tilelink2 WidthWidget: Gets must have their mask adjusted (#353)
|
2016-09-27 14:06:02 -07:00 |
Xbar.scala
|
tilelink2 Xbar: decouple ready from valid (#338)
|
2016-09-23 16:24:29 -07:00 |