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AddressDecoder.scala
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tilelink2 AddressDecoder: validate output of optimization
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2016-09-16 16:09:00 -07:00 |
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Arbiter.scala
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tilelink2 Xbar: decouple ready from valid (#338)
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2016-09-23 16:24:29 -07:00 |
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AtomicAutomata.scala
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tilelink2 Atomics: optimize the sign-extension circuit
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2016-09-22 15:18:54 -07:00 |
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Buffer.scala
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tilelink2: change adapters to use TLAdapter(params, defaults)(node)
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2016-09-22 20:52:46 -07:00 |
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Bundles.scala
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tilelink2: don't use chisel3 namespace (#355)
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2016-09-27 14:44:26 -07:00 |
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Crossing.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Edges.scala
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Tl2 addr width0 (#346)
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2016-09-26 17:00:03 -07:00 |
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Example.scala
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RegMapper: regmap(...) now takes BYTE addresses
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2016-09-22 20:52:46 -07:00 |
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Fragmenter.scala
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tilelink2: change adapters to use TLAdapter(params, defaults)(node)
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2016-09-22 20:52:46 -07:00 |
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Fuzzer.scala
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tilelink2: don't use chisel3 namespace (#355)
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2016-09-27 14:44:26 -07:00 |
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HintHandler.scala
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tilelink2: change adapters to use TLAdapter(params, defaults)(node)
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2016-09-22 20:52:46 -07:00 |
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IntNodes.scala
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tilelink2 Nodes: split connect into eager and lazy halves
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2016-09-22 15:18:50 -07:00 |
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LazyModule.scala
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tilelink2 LazyModule: output GraphML of the bus
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2016-09-26 14:35:46 -07:00 |
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Legacy.scala
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tilelink2 Legacy: convert TL1 atomic operand size
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2016-09-22 15:18:54 -07:00 |
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Monitor.scala
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tilelink2 Monitor: work around for firrtl/verilator performance issue
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2016-09-22 15:18:54 -07:00 |
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Nodes.scala
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tilelink2 Nodes: expose connectivity in RootNode
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2016-09-26 14:35:46 -07:00 |
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Parameters.scala
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tilelink2 AddressSet: add .misaligned(low, size) helper method (#345)
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2016-09-26 16:01:09 -07:00 |
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RAMModel.scala
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tilelink2: don't use chisel3 namespace (#355)
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2016-09-27 14:44:26 -07:00 |
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RegField.scala
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RegField: remove obsolete split method
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2016-09-22 20:52:47 -07:00 |
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RegMapper.scala
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tilelink2: don't use chisel3 namespace (#355)
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2016-09-27 14:44:26 -07:00 |
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RegisterCrossing.scala
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crossing: Remove reset from the logic in Register Crossing because it is no longer needed when the underlying crossings are asynchronously reset. Update the order of operations
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2016-09-27 13:36:28 -07:00 |
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RegisterRouter.scala
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tilelink2 RegisterRouter: minLatency is never more than 1
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2016-09-22 15:51:15 -07:00 |
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RegisterRouterTest.scala
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[tilelink2] Make map generation in RRTests a def so that multiple RRTests can be instantiated as part of the same unit test suite. (#356)
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2016-09-27 18:06:21 -07:00 |
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SRAM.scala
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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TLNodes.scala
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tilelink2 Parameters: include a minLatency parameter for optimization
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2016-09-22 15:18:54 -07:00 |
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WidthWidget.scala
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tilelink2 WidthWidget: Gets must have their mask adjusted (#353)
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2016-09-27 14:06:02 -07:00 |
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Xbar.scala
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tilelink2 Xbar: decouple ready from valid (#338)
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2016-09-23 16:24:29 -07:00 |
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package.scala
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tilelink2 Atomics: optimize the sign-extension circuit
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2016-09-22 15:18:54 -07:00 |
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