| .. |
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AddressDecoder.scala
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tilelink2 AddressDecoder: validate output of optimization
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2016-09-16 16:09:00 -07:00 |
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Arbiter.scala
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tilelink2: add a general-purpose Arbiter
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2016-09-22 15:18:53 -07:00 |
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AtomicAutomata.scala
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tilelink2 Atomics: support arithmetic atomics
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2016-09-22 15:18:54 -07:00 |
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Buffer.scala
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tilelink2 Buffer: increase the minLatency on ports
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2016-09-22 15:18:54 -07:00 |
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Bundles.scala
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tilelink2 Bundles: add 1-way snoop bundles
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2016-09-22 15:14:20 -07:00 |
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Crossing.scala
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[tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions.
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2016-09-14 17:43:07 -07:00 |
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Edges.scala
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tilelink2: differentiate fast/safe address lookup cases
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2016-09-17 17:04:18 -07:00 |
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Example.scala
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Merge remote-tracking branch 'origin/master' into black_box_regs
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2016-09-09 13:12:52 -07:00 |
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Fragmenter.scala
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tilelink2: most adapters can wipe away latency
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2016-09-22 15:18:54 -07:00 |
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Fuzzer.scala
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tilelink2 Fuzzer: work around for firrtl/verilator performance issue
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2016-09-22 15:18:54 -07:00 |
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HintHandler.scala
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tilelink2: most adapters can wipe away latency
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2016-09-22 15:18:54 -07:00 |
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IntNodes.scala
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tilelink2 Nodes: split connect into eager and lazy halves
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2016-09-22 15:18:50 -07:00 |
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LazyModule.scala
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tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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2016-09-08 23:06:59 -07:00 |
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Legacy.scala
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tilelink2 Legacy: convert TL1 atomic operand size
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2016-09-22 15:18:54 -07:00 |
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Monitor.scala
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tilelink2 Monitor: work around for firrtl/verilator performance issue
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2016-09-22 15:18:54 -07:00 |
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Nodes.scala
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tilelink2 Nodes: split connect into eager and lazy halves
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2016-09-22 15:18:50 -07:00 |
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package.scala
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tilelink2 Fuzzer: work around for firrtl/verilator performance issue
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2016-09-22 15:18:54 -07:00 |
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Parameters.scala
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tilelink2 Parameters: include a minLatency parameter for optimization
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2016-09-22 15:18:54 -07:00 |
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RAMModel.scala
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tilelink2 RAMModel: exploit latency to remove bypass
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2016-09-22 15:18:54 -07:00 |
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RegField.scala
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RegField: separate UInt=>bytes and bytes=>regs
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2016-09-16 14:24:28 -07:00 |
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RegisterCrossing.scala
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Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable
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2016-09-14 17:50:17 -07:00 |
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RegisterRouter.scala
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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RegisterRouterTest.scala
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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RegMapper.scala
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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SRAM.scala
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tilelink2: specify the minLatency for SRAM+RR
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2016-09-22 15:18:54 -07:00 |
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TLNodes.scala
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tilelink2 Parameters: include a minLatency parameter for optimization
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2016-09-22 15:18:54 -07:00 |
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WidthWidget.scala
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tilelink2: most adapters can wipe away latency
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2016-09-22 15:18:54 -07:00 |
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Xbar.scala
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tilelink2 Parameters: include a minLatency parameter for optimization
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2016-09-22 15:18:54 -07:00 |
