riscv/rocket-chip
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533 Commits

Author SHA1 Message Date
Henry Cook
5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
Henry Cook
10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
Wesley W. Terpstra
5b594ced29 Plic: support 0 interrupts gracefully 2016-11-18 18:07:44 -08:00
Wesley W. Terpstra
03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
Wesley W. Terpstra
37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra
e5febcfa33 rocketchip: there are no more useful parameters to dump 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra
119ccae9af rocketchip: don't use explicit cde namespace 2016-11-18 14:31:42 -08:00
Henry Cook
94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
Henry Cook
960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
Wesley W. Terpstra
dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
Henry Cook
24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
Henry Cook
479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00
Henry Cook
1f51564577 [rocket] dcache probe ack data bugfix 2016-11-16 14:25:21 -08:00
Wesley W. Terpstra
5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id 2016-11-16 12:16:25 -08:00
Wesley W. Terpstra
10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Wesley W. Terpstra
ab3dafb8bc Monitor: restore Probe&Acquire checks 2016-11-14 15:36:52 -08:00
Wesley W. Terpstra
385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
Henry Cook
c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Henry Cook
b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) 2016-11-11 18:34:48 -08:00
Henry Cook
71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
Henry Cook
afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Wesley W. Terpstra
9d77e34bee tilelink2 Filter: make transfer cap robust against large filters 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
b8df59f43b tilelink2 Broadcast: support "bufferless" implementation 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
14800f8fb4 tilelink2 Broadcast: only support caching readable devices 2016-11-04 13:35:36 -07:00
Wesley W. Terpstra
0f3947bb86 tilelink2 Broadcast: add special case handling for 0 cached clients 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
ba3c83287f tilelink2 Xbar: merge the AddressSets of fractured managers 2016-11-03 22:18:28 -07:00
Wesley W. Terpstra
55326c29bb tilelink2: Filter adapter removes some of the address space 2016-11-03 22:18:23 -07:00
Wesley W. Terpstra
86ba94781b tilelink2: broadcast coherence manager 2016-11-03 14:37:19 -07:00
Wesley W. Terpstra
d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager 2016-11-03 14:37:17 -07:00
Wesley W. Terpstra
ed4224dde4 tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull 
If we send out the PutFull portion of an AMO, the slave is allowed
to respond with AccessAck on the same cycle. In this case, we are
still in the AMO state, but must still match the D response.
 2016-10-31 15:17:10 -07:00
Wesley W. Terpstra
a12fea51e8 Plic: skip reserved interrupt in interrupt map printout 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
ba529c3716 rocketchip: use TileLink2 interrupts 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
015c3b862a diplomacy: print out bus widths on edges in agent graph 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
0cc00e7616 regressions: test scratchpad 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
d2e9fa8ec6 Plic: remove path from ready to bits 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
545154c1c3 groundtest: make it happy with TL2 addressing 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
9a26cb7ec7 Debug: mark the debug device executable 2016-10-31 11:42:47 -07:00
Wesley W. Terpstra
89139a9492 Plic: split constants from variables used in config string 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
11121b6f4c rocket: convert scratchpad to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
f8a0829134 rocketchip: remove clint; it moves into coreplex 2016-10-31 11:42:13 -07:00
Megan Wachs
5090ff945b DebugModule: Be more paranoid about addressing corner cases. 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
b99662796d PLIC: converted to TL2 2016-10-31 11:42:13 -07:00
Wesley W. Terpstra
bddfa4d69b Debug: make address configurable 2016-10-31 11:42:13 -07:00
Megan Wachs
10d084b9f3 DebugModule: Use the power of RegisterRouter to simplify the DebugROM code. 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
650f6fb23f diplomacy: add BlindNodes for use as external ports 2016-10-31 11:41:18 -07:00
Wesley W. Terpstra
0edcd3304a diplomacy Nodes: leave flipping to the MixedNode implementation 2016-10-31 11:41:18 -07:00
Megan Wachs
d530ef7236 DebugModule: translate to TL2 with {32,64}-bit XLen width 2016-10-31 11:41:18 -07:00
Howard Mao
f0e9a2a081 Fix PutBlock after Release bug 
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.

The fix is to make the outer release block if there are pending
inner PutBlock beats.
 2016-10-28 18:26:34 -07:00