Wesley W. Terpstra
248acbd1b4
tilelink2: add a generic TL2 atomic evaulation unit
2017-04-14 15:13:39 -07:00
Wesley W. Terpstra
1c36ab8bf7
Fragmenter: forbid multiple sink IDs
...
Otherwise a slave might respond with different IDs for different
requests and the Fragmenter would violate the requirement that
control signals remain unchanged for a burst.
2017-04-11 12:38:00 -07:00
Wesley W. Terpstra
84dc2ae822
CacheCork: remove probe support
2017-04-11 12:34:18 -07:00
Wesley W. Terpstra
71bf929505
maskgen: support wider granularity result ( #665 )
...
Sometimes it is useful to generate a mask with bits that correspond
to a larger unit than bytes.
2017-04-09 20:06:23 -07:00
Megan Wachs
43804726ac
tilelink2: more helpful requirement message
2017-03-27 21:05:05 -07:00
Wesley W. Terpstra
5b339b6bbd
tilelink2 Monitor: catch incorrect use of source ID
2017-03-27 16:30:46 -07:00
Henry Cook
797c18b8db
Make some requirement failures more verbose ( #608 )
...
* tilelink: verbose requires in xbar
* diplomacy: verbose requires
2017-03-23 21:55:11 -07:00
Wesley W. Terpstra
bd08f10816
tilelink2: make sink ids optional ( #607 )
...
* tilelink2: make sink ids optional
* CacheCork: add a special-case for 1 sink id
2017-03-23 18:19:04 -07:00
Andrew Waterman
76f083b469
FIFOFixer: Not all D-channel messages are A-channel responses
2017-03-21 14:17:38 -07:00
Wesley W. Terpstra
198afddb4b
tilelink2: add the FIFOFixer
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
c33f31dd3c
tilelink2 RAMModel: weaken fifo requirement check
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
930438adba
tilelink2 SourceShrinker: destroy FIFO behaviour
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
fd521c56a6
tilelink2: add client-side FIFO parameterization
2017-03-21 11:16:51 -07:00
Wesley W. Terpstra
4eef317e84
RegisterRouter: support devices with gaps
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
431cb41e27
tilelink2 Parameters: clarify client minLatency is B=>C, not D=>E
2017-03-20 14:49:22 -07:00
Wesley W. Terpstra
04892fea01
Monitor: support early ack
2017-03-20 14:49:19 -07:00
Wesley W. Terpstra
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
Wesley W. Terpstra
778e189bba
Monitor: ProbeAckData and ReleaseData may carry an error
2017-03-20 11:44:13 -07:00
Wesley W. Terpstra
48c7aed4e1
Monitor: any probe supported by the client is legal
2017-03-20 11:34:19 -07:00
Wesley W. Terpstra
c9459fe4eb
tilelink2 Xbar: don't use unnecessary ports
2017-03-19 17:02:24 -07:00
Wesley W. Terpstra
7971947d6c
tilelink2 Monitor: don't inspect bits if valid is forbidden
2017-03-19 16:34:23 -07:00
Wesley W. Terpstra
db55a1d755
Fragmenter: fix a bug when underlying device supports larger bursts ( #589 )
2017-03-17 11:00:49 -07:00
Wesley W. Terpstra
882a7ff8ff
TLToAPB: use the now standard aFlow parameter name
2017-03-16 15:34:59 -07:00
Wesley W. Terpstra
ca2c709d29
TLBuffer: move TLBufferParams to diplomacy.BufferParams
2017-03-16 15:19:36 -07:00
Wesley W. Terpstra
778c8a5c97
ToAHB: appease AHB VIP
2017-03-16 15:17:05 -07:00
Wesley W. Terpstra
604a164b97
TLToAHB: rename parameter to aFlow
2017-03-16 15:10:54 -07:00
Wesley W. Terpstra
bb49575368
ahb: rewrote TLToAHB to avoid retracting requests on stall
2017-03-16 14:36:30 -07:00
Wesley W. Terpstra
d98fd942f1
tilelink2: optimize the supportsX check circuits
2017-03-14 18:34:17 -07:00
Wesley W. Terpstra
3c5c877409
tilelink2: make TLBuffer API more flexible
2017-03-14 14:06:18 -07:00
Wesley W. Terpstra
6fc3ec3d63
tileink2: add a TestRAM; a zero-delay RAM useful for testing
...
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
2017-03-14 14:06:17 -07:00
Henry Cook
bb0390630c
Merge branch 'master' into priv-1.10
2017-03-13 21:40:12 -07:00
Wesley W. Terpstra
eaf474a081
LFSR: use random intial value of the start register
...
We just need to make sure it doesn't initialize randomly stuck at 0.
2017-03-13 13:17:52 -07:00
Henry Cook
1a3fec61c0
Merge branch 'master' into priv-1.10
2017-03-13 11:59:18 -07:00
Wesley W. Terpstra
d2da33e4b1
Fuzzer: use different LFSR seeds based on simulator seed
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
bb6108abd5
Tests: include more random delays
2017-03-11 02:53:43 -08:00
Wesley W. Terpstra
0c7fb87390
TLDelayer: insert noise on invalid cycles
2017-03-11 02:53:43 -08:00
Jacob Chang
1c6dde8c15
Make parameters for TLToAHB and TLToAXI4 accessable ( #581 )
2017-03-10 22:26:38 -08:00
Henry Cook
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
Wesley W. Terpstra
d3c5318714
build: remove the now obsolete config string
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
93ca555c20
IntXing: support configurable sync depth
2017-03-02 21:19:23 -08:00
Wesley W. Terpstra
38489ad9b0
tilelink2: bring IntNode parameters up to the current standard
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
cfd367248f
rocketchip: add blind ports to DTS
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
9a5e2e038b
uncore: add DTS meta-data for devices
2017-03-02 21:19:22 -08:00
Wesley W. Terpstra
7f6a250dbf
tilelink2: add hooks for Resources
2017-03-02 21:19:19 -08:00
Henry Cook
6958f05a85
Merge remote-tracking branch 'origin/master' into periphery-adjustments
2017-02-27 19:40:55 -08:00
Andrew Waterman
dfa61bc487
Standardize Data.holdUnless and SeqMem.readAndHold
...
- Make API more idiomatic (x holdUnless y, instead of holdUnless(x, y))
- Add new SeqMem API, readAndHold, which corresponds to most common
use of holdUnless
2017-02-25 03:07:49 -08:00
Wesley W. Terpstra
c01aec9259
tilelink2: support unused IntXing
2017-02-22 18:41:06 -08:00
Wesley W. Terpstra
735e4f8ed6
diplomacy: use HeterogeneousBag instead of Vec
...
This makes it possible for the bundles to have different widths.
Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities. This would mean that if
you had two source[] fields, they end up the same.
2017-02-22 17:05:22 -08:00
Wesley W. Terpstra
5045696f92
TLRational: test all corners
...
In order to ensure that verilator is happy, we launch both clocks from a
clock divider. Sadly, it does not follow the spec wrt. derived clocks.
See the verilator manual section on "Generated Clocks".
2017-02-17 14:44:31 +01:00
Wesley W. Terpstra
924afebbd9
tilelink2: make TLRational have configurable direction
2017-02-17 13:59:54 +01:00