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rocket-chip/src/main/scala/uncore/tilelink2
2017-03-27 16:30:46 -07:00
..
Arbiter.scala copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
AsyncCrossing.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
AtomicAutomata.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
Broadcast.scala rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Buffer.scala TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Bundles.scala rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
CacheCork.scala tilelink2: make sink ids optional (#607) 2017-03-23 18:19:04 -07:00
Delayer.scala TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Edges.scala tilelink2: define is{Request,Response} based on spec 2017-03-20 13:41:02 -07:00
Example.scala uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
FIFOFixer.scala FIFOFixer: Not all D-channel messages are A-channel responses 2017-03-21 14:17:38 -07:00
Filter.scala uncore: switch to new diplomacy Node API 2017-01-29 15:54:45 -08:00
Fragmenter.scala Fragmenter: fix a bug when underlying device supports larger bursts (#589) 2017-03-17 11:00:49 -07:00
Fuzzer.scala LFSR: use random intial value of the start register 2017-03-13 13:17:52 -07:00
HintHandler.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
IntNodes.scala IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Isolation.scala tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Legacy.scala diplomacy: make config.Parameters available in bundle connect() 2016-12-07 12:24:01 -08:00
Metadata.scala rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Monitor.scala tilelink2 Monitor: catch incorrect use of source ID 2017-03-27 16:30:46 -07:00
Nodes.scala diplomacy: use HeterogeneousBag instead of Vec 2017-02-22 17:05:22 -08:00
package.scala Standardize Data.holdUnless and SeqMem.readAndHold 2017-02-25 03:07:49 -08:00
Parameters.scala tilelink2: make sink ids optional (#607) 2017-03-23 18:19:04 -07:00
RAMModel.scala tilelink2 RAMModel: weaken fifo requirement check 2017-03-21 11:16:51 -07:00
RationalCrossing.scala TLRational: test all corners 2017-02-17 14:44:31 +01:00
RegisterRouter.scala RegisterRouter: support devices with gaps 2017-03-20 14:49:22 -07:00
RegisterRouterTest.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
Repeater.scala copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
SourceShrinker.scala tilelink2 SourceShrinker: destroy FIFO behaviour 2017-03-21 11:16:51 -07:00
SRAM.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
TestRAM.scala tileink2: add a TestRAM; a zero-delay RAM useful for testing 2017-03-14 14:06:17 -07:00
ToAHB.scala ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
ToAPB.scala TLToAPB: use the now standard aFlow parameter name 2017-03-16 15:34:59 -07:00
ToAXI4.scala Make parameters for TLToAHB and TLToAXI4 accessable (#581) 2017-03-10 22:26:38 -08:00
WidthWidget.scala Tests: include more random delays 2017-03-11 02:53:43 -08:00
Xbar.scala Make some requirement failures more verbose (#608) 2017-03-23 21:55:11 -07:00
Zero.scala uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00