riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,266 Commits 1 Branch 0 Tags 13 MiB
0280a1f218
Commit Graph

5266 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Howard Mao
af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Howard Mao
ee624b1c6e make NastiSmallTest a bit more intensive 2016-07-05 17:31:51 -07:00
Howard Mao
96f09003f2 use options for NastiWriteDataChannel write mask 2016-07-05 16:03:25 -07:00
Albert Ou
4c07aedfad Rewrite BRAMSlave to infer a single BRAM instance 2016-07-05 14:21:21 -07:00
Howard Mao
8c5fd86f9b fix tracegen module and scripts 2016-07-05 13:50:17 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00
Howard Mao
06ed9c5794 add a single-entry queue in front of acquire and release for bufferless broadcast hub 2016-07-05 12:08:22 -07:00
Howard Mao
67bac383e3 hopefully fixed last bugs in Bufferless 2016-07-05 12:08:22 -07:00
Howard Mao
a35388bc27 fix merging of same xact ID puts/gets 2016-07-05 12:08:22 -07:00
Howard Mao
51f7bf1511 fix Bufferless voluntary release issue 2016-07-05 12:08:22 -07:00
Howard Mao
afc51c4a35 make sure TL -> NASTI converter handles multibeat transactions properly 2016-07-05 12:08:22 -07:00
Andrew Waterman
ebefe57036 simplify BTB fetchWidth=1 special case 2016-07-04 23:43:47 -07:00
Howard Mao
61a44dcfc3 add regression test for L1 voluntary releases 2016-07-04 17:02:24 -07:00
Andrew Waterman
85808f8cbb Clean up PseudoLRU code 2016-07-02 15:09:12 -07:00
Andrew Waterman
2d325df60c Improve PTW simulation performance 2016-07-02 14:34:18 -07:00
Andrew Waterman
5aa8ef1855 Remove invalidation support from BTB 
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
 2016-07-02 14:27:29 -07:00
Andrew Waterman
663002ec0c Improve TLB simulation performance 2016-07-02 14:26:05 -07:00
Howard Mao
af51b6f363 bump groundtest and uncore 2016-07-01 18:13:46 -07:00
Howard Mao
b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao
7f0a583515 timeout for Nasti tests 2016-07-01 18:11:44 -07:00
Howard Mao
caa9ca24b9 NASTI -> TL converter also uses ID mapper 2016-07-01 18:11:29 -07:00
Howard Mao
37599fb0c9 fix use of width adapter in NastiConverterTest 2016-07-01 17:05:41 -07:00
Wesley W. Terpstra
39bee5198d Nasti Puts: decode wmask to determine addr_byte() and op_size() 
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
 2016-07-01 16:49:32 -07:00
Howard Mao
e163a23583 fix another bug in Widener 2016-07-01 16:24:48 -07:00
Howard Mao
10a46a36ae fix full_addr() function in TileLink 2016-07-01 15:17:41 -07:00
Howard Mao
e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao
61e3e5b45a more WIP on fixing Bufferless 2016-06-30 18:29:51 -07:00
Howard Mao
0eedffa82f WIP: Fix BufferlessBroadcastHub 2016-06-30 18:29:51 -07:00
Howard Mao
600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao
ce46f523c9 make sure Widener uses proper parameters to generate acquire/grant 2016-06-30 18:17:16 -07:00
Howard Mao
f46efb671d add multi-transaction timer and add to Comparator 2016-06-30 17:39:10 -07:00
Howard Mao
a0b1772404 change TileLinkWidthAdapter interface 2016-06-30 15:50:23 -07:00
Howard Mao
e83b3d2472 turn up generator memory timeout 2016-06-29 10:57:31 -07:00
Howard Mao
39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00
Howard Mao
a39a0c0ec4 .prm is output of chisel stage, not firrtl stage 2016-06-28 17:34:37 -07:00
Howard Mao
b30e0254ee fix Makefrag to detect all Chisel source files 2016-06-28 16:39:10 -07:00
Howard Mao
ebef4ddad0 remove mention of HTIF from README 2016-06-28 15:23:32 -07:00
Andrew Waterman
f1cbb2ff77 Turn up optimization for Verilator compilation 2016-06-28 14:12:46 -07:00
Howard Mao
74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Howard Mao
a9e0a5e2df changes to imports after uncore refactor 2016-06-28 14:09:31 -07:00
Howard Mao
80670c08d7 changes to imports after uncore refactor 2016-06-28 13:15:56 -07:00
Howard Mao
9feca99d5d make PutBlock wmask argument match Put 2016-06-28 13:10:46 -07:00
Howard Mao
b936aa9826 refactor uncore files into separate packages 2016-06-28 13:10:46 -07:00
Andrew Waterman
c10691b616 Don't take interrupts on instructions in branch shadow 
In situations like

       j 1f
       nop
    1: nop

the interrupt could be taken on the first nop.
 2016-06-28 12:47:49 -07:00
Andrew Waterman
a70dee17ea Make RoCC energy-saving logic mirror same for D$ 2016-06-28 12:47:45 -07:00
Andrew Waterman
c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Andrew Waterman
97e74aec3a Merge RTC and PRCI 2016-06-27 23:06:07 -07:00
Howard Mao
d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao
f438e7048c no longer need DummyCache since tiles no longer require cached interface 2016-06-27 16:32:06 -07:00