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riscv/rocket-chip
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d0b46c5b8ff1b057b752928ccd9907604dd3b83f
rocket-chip/src/main/scala
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Schuyler EldridgeandHenry Cook d0b46c5b8f Align RoCCIO with new cloneType (#1270)
- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-06 17:53:51 -08:00
..
amba
coreplex => subsystem
2018-02-21 14:42:24 -08:00
config
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
devices
Merge pull request #1263 from freechipsproject/sim_jtag_reset
2018-03-06 11:28:51 -08:00
diplomacy
diplomacy: put full module + instance path into graphml Description
2018-02-21 14:43:47 -08:00
groundtest
subsystem: XSubsystemModule => XSubsystemModuleImp
2018-02-21 14:52:59 -08:00
interrupts
diplomacy: provide a val name for all LazyModule constructions
2017-12-01 11:28:21 -08:00
jtag
Fix JTAG cover description (#1248)
2018-02-23 12:13:31 -08:00
regmapper
DescribedReg: fix some imports
2018-03-06 11:02:10 -08:00
rocket
BUE: more verbose register descriptions
2018-03-05 12:02:42 -08:00
subsystem
subsystem: add some inter-wrapper buffer params
2018-02-23 15:31:18 -08:00
system
subsystem: XSubsystemModule => XSubsystemModuleImp
2018-02-21 14:52:59 -08:00
tile
Align RoCCIO with new cloneType (#1270)
2018-03-06 17:53:51 -08:00
tilelink
Bump chisel and firrtl (#1232)
2018-03-01 15:19:12 -08:00
unittest
coreplex => subsystem
2018-02-21 14:42:24 -08:00
util
DescribedReg: move to regmapper
2018-03-05 16:12:14 -08:00
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