2012-10-23 21:51:37 +02:00
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package referencechip
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2012-10-09 22:05:56 +02:00
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import Chisel._
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import uncore._
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import rocket._
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2013-01-25 08:56:45 +01:00
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import rocket.Util._
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2012-10-09 22:05:56 +02:00
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import ReferenceChipBackend._
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import scala.collection.mutable.ArrayBuffer
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import scala.collection.mutable.HashMap
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2013-08-03 00:02:09 +02:00
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object DummyTopLevelConstants {
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2013-08-12 19:46:22 +02:00
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val NTILES = 1
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2013-07-25 08:28:43 +02:00
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val NBANKS = 1
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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2013-09-21 15:40:23 +02:00
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val HAS_FPU = true
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2013-08-03 00:02:09 +02:00
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val NL2_REL_XACTS = 1
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2013-08-24 22:20:38 +02:00
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val NL2_ACQ_XACTS = 7
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2013-08-03 00:02:09 +02:00
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val NMSHRS = 2
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2012-12-12 09:06:14 +01:00
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}
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2013-08-24 22:20:38 +02:00
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import DummyTopLevelConstants._
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2012-10-09 22:05:56 +02:00
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object ReferenceChipBackend {
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2013-08-12 19:46:22 +02:00
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val initMap = new HashMap[Module, Bool]()
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2012-10-09 22:05:56 +02:00
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}
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class ReferenceChipBackend extends VerilogBackend
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{
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2013-09-20 05:12:10 +02:00
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initMap.clear()
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2012-10-09 22:05:56 +02:00
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override def emitPortDef(m: MemAccess, idx: Int) = {
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val res = new StringBuilder()
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for (node <- m.mem.inputs) {
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if(node.name.contains("init"))
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res.append(" .init(" + node.name + "),\n")
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}
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(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
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}
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2013-08-12 19:46:22 +02:00
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def addMemPin(c: Module) = {
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for (node <- Module.nodes) {
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2012-10-19 02:51:41 +02:00
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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2013-04-20 10:36:32 +02:00
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connectMemPin(c, node.component, node)
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2012-10-09 22:05:56 +02:00
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}
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}
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}
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2013-08-12 19:46:22 +02:00
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def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
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2012-10-09 22:05:56 +02:00
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var isNewPin = false
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val compInitPin =
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if (initMap.contains(c)) {
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initMap(c)
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} else {
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isNewPin = true
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2013-09-20 05:12:10 +02:00
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val res = Bool(INPUT)
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res.isIo = true
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res
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2012-10-09 22:05:56 +02:00
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}
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p.inputs += compInitPin
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if (isNewPin) {
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compInitPin.setName("init")
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c.io.asInstanceOf[Bundle] += compInitPin
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2013-04-20 09:38:01 +02:00
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compInitPin.component = c
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2012-10-09 22:05:56 +02:00
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initMap += (c -> compInitPin)
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connectMemPin(topC, c.parent, compInitPin)
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}
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}
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2013-08-12 19:46:22 +02:00
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def addTopLevelPin(c: Module) = {
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2012-10-09 22:05:56 +02:00
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val init = Bool(INPUT)
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2013-09-20 05:12:10 +02:00
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init.isIo = true
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2012-10-09 22:05:56 +02:00
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init.setName("init")
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init.component = c
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c.io.asInstanceOf[Bundle] += init
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initMap += (c -> init)
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}
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2013-08-12 19:46:22 +02:00
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transforms += ((c: Module) => addTopLevelPin(c))
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transforms += ((c: Module) => addMemPin(c))
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2013-09-20 05:12:10 +02:00
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transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
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2012-10-09 22:05:56 +02:00
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}
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2013-08-12 19:46:22 +02:00
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class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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2012-10-09 22:05:56 +02:00
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{
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2013-08-03 00:02:09 +02:00
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implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
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2012-10-09 22:05:56 +02:00
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val io = new Bundle {
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2013-08-12 19:46:22 +02:00
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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2013-01-07 23:19:55 +01:00
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val htif = (new TileLinkIO).flip
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2013-08-12 19:46:22 +02:00
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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2013-08-03 00:02:09 +02:00
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val mem = new ioMem
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2012-10-19 02:51:41 +02:00
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val mem_backup = new ioMemSerialized(htif_width)
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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}
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2013-08-12 19:46:22 +02:00
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val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
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val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
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2013-09-21 15:40:23 +02:00
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val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
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//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
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2013-08-12 19:46:22 +02:00
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val mem_serdes = Module(new MemSerdes(htif_width))
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2012-10-09 22:05:56 +02:00
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2013-08-03 00:02:09 +02:00
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require(clientEndpoints.length == ln.nClients)
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2013-08-12 19:46:22 +02:00
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val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
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val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
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2013-03-20 22:11:54 +01:00
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net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
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2013-08-03 00:02:09 +02:00
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masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
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2013-03-20 22:11:54 +01:00
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2013-08-12 19:46:22 +02:00
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val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
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2013-08-03 00:02:09 +02:00
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if(ln.nMasters > 1) {
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2013-08-12 19:46:22 +02:00
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val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
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2013-03-20 22:11:54 +01:00
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arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
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conv.io.uncached <> arb.io.out
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} else {
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conv.io.uncached <> masterEndpoints.head.io.master
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2012-10-09 22:05:56 +02:00
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}
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2013-03-20 22:11:54 +01:00
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llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES)
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conv.io.mem.resp <> llc.io.cpu.resp
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2012-10-09 22:05:56 +02:00
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// mux between main and backup memory ports
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2013-08-12 19:46:22 +02:00
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val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
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2012-10-09 22:05:56 +02:00
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
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io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
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mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
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2013-08-12 19:46:22 +02:00
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val mem_dataq = Module(new Queue(new MemData, REFILL_CYCLES))
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2012-10-09 22:05:56 +02:00
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mem_dataq.io.enq <> llc.io.mem.req_data
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mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
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io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
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io.mem.req_data.bits := mem_dataq.io.deq.bits
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mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
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llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
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2013-05-02 13:58:43 +02:00
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io.mem.resp.ready := Bool(true)
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2012-10-09 22:05:56 +02:00
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llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
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io.mem_backup <> mem_serdes.io.narrow
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}
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2013-08-25 00:47:42 +02:00
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case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
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2013-08-03 00:02:09 +02:00
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2013-08-12 19:46:22 +02:00
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class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
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2012-10-09 22:05:56 +02:00
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{
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2013-08-03 00:02:09 +02:00
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implicit val tl = conf.tl
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2012-10-09 22:05:56 +02:00
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val io = new Bundle {
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2013-01-07 23:19:55 +01:00
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val host = new HostIO(htif_width)
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2013-08-03 00:02:09 +02:00
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val mem = new ioMem
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2013-08-12 19:46:22 +02:00
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val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
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val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
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val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
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2012-10-19 02:51:41 +02:00
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val mem_backup = new ioMemSerialized(htif_width)
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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}
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2013-09-09 23:31:18 +02:00
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val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
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2013-08-12 19:46:22 +02:00
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val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
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2013-08-03 00:02:09 +02:00
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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2012-10-19 02:51:41 +02:00
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htif.io.cpu <> io.htif
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2013-08-03 00:02:09 +02:00
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outmemsys.io.mem <> io.mem
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2012-10-09 22:05:56 +02:00
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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2013-03-20 22:11:54 +01:00
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// Add networking headers and endpoint queues
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2013-08-12 19:46:22 +02:00
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def convertAddrToBank(addr: Bits): UInt = {
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2013-08-03 00:02:09 +02:00
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require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
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addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
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2013-04-23 02:38:13 +02:00
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}
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2013-03-20 22:11:54 +01:00
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(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
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case ((outer, client), i) =>
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2013-08-03 00:02:09 +02:00
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outer.acquire <> TileLinkHeaderAppender(client.acquire, i, conf.nBanks, convertAddrToBank _)
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outer.release <> TileLinkHeaderAppender(client.release, i, conf.nBanks, convertAddrToBank _)
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2013-03-20 22:11:54 +01:00
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val grant_ack_q = Queue(client.grant_ack)
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outer.grant_ack.valid := grant_ack_q.valid
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outer.grant_ack.bits := grant_ack_q.bits
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2013-08-12 19:46:22 +02:00
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outer.grant_ack.bits.header.src := UInt(i)
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2013-03-20 22:11:54 +01:00
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grant_ack_q.ready := outer.grant_ack.ready
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client.grant <> Queue(outer.grant, 1, pipe = true)
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client.probe <> Queue(outer.probe)
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}
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2012-10-09 22:05:56 +02:00
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// pad out the HTIF using a divided clock
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2013-08-12 19:46:22 +02:00
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val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) })
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2013-01-25 08:56:45 +01:00
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hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
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hio.io.set_divisor.bits := htif.io.scr.wdata
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htif.io.scr.rdata(63) := hio.io.divisor
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2012-10-09 22:05:56 +02:00
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hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
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hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
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htif.io.host.out.ready := hio.io.out_fast.ready
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outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
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io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
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io.host.out.bits := hio.io.out_slow.bits
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io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
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hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
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val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
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hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
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hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
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io.host.in.ready := hio.io.in_slow.ready
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outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
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outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
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htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
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htif.io.host.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
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2012-10-19 02:51:41 +02:00
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io.host.clk := hio.io.clk_slow
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2013-08-16 01:37:58 +02:00
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io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
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2012-10-09 22:05:56 +02:00
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}
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2013-08-03 00:02:09 +02:00
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class TopIO(htifWidth: Int) extends Bundle {
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val host = new HostIO(htifWidth)
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val mem = new ioMem
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}
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class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
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2012-10-09 22:05:56 +02:00
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val mem_backup_en = Bool(INPUT)
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2012-10-23 12:31:34 +02:00
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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val out_mem_ready = Bool(INPUT)
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val out_mem_valid = Bool(OUTPUT)
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2012-10-09 22:05:56 +02:00
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}
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2013-08-12 19:46:22 +02:00
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class MemDessert extends Module {
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2012-10-19 02:51:41 +02:00
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val io = new MemDesserIO(HTIF_WIDTH)
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2013-08-12 19:46:22 +02:00
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val x = Module(new MemDesser(HTIF_WIDTH))
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2012-10-19 02:51:41 +02:00
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io.narrow <> x.io.narrow
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io.wide <> x.io.wide
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}
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2013-08-12 19:46:22 +02:00
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class Top extends Module {
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2012-10-09 22:05:56 +02:00
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val co = if(ENABLE_SHARING) {
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if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
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else new MSICoherence
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} else {
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if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
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else new MICoherence
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}
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2013-08-03 00:02:09 +02:00
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implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
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implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
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implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
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2013-08-25 00:47:42 +02:00
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implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
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2012-10-19 02:51:41 +02:00
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|
2013-08-03 00:02:09 +02:00
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val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
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val dc = DCacheConfig(128, 4, ntlb = 8,
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nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
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|
|
val rc = RocketConfiguration(tl, ic, dc,
|
2013-09-15 13:25:26 +02:00
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|
fpu = HAS_FPU)
|
2013-08-03 00:02:09 +02:00
|
|
|
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|
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val io = new VLSITopIO(HTIF_WIDTH)
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|
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|
2013-08-12 19:46:22 +02:00
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
|
2013-08-16 02:07:13 +02:00
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|
|
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
|
2013-08-12 19:46:22 +02:00
|
|
|
val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
|
2012-10-09 22:05:56 +02:00
|
|
|
|
2013-08-03 00:02:09 +02:00
|
|
|
for (i <- 0 until uc.nTiles) {
|
2012-10-09 22:05:56 +02:00
|
|
|
val hl = uncore.io.htif(i)
|
|
|
|
val tl = uncore.io.tiles(i)
|
2013-01-07 23:19:55 +01:00
|
|
|
val il = uncore.io.incoherent(i)
|
2012-10-19 02:51:41 +02:00
|
|
|
|
2012-12-13 01:41:21 +01:00
|
|
|
resetSigs(i) := hl.reset
|
|
|
|
val tile = tileList(i)
|
2013-03-20 22:11:54 +01:00
|
|
|
tile.io.tilelink <> tl
|
|
|
|
il := hl.reset
|
2013-08-16 01:37:58 +02:00
|
|
|
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
|
2013-09-13 02:03:38 +02:00
|
|
|
tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
|
|
|
|
tile.io.host.id := i
|
|
|
|
hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
|
|
|
|
hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
|
|
|
|
tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
|
2012-10-09 22:05:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
io.host <> uncore.io.host
|
|
|
|
|
2012-10-23 12:31:34 +02:00
|
|
|
uncore.io.mem_backup.resp.valid := io.in_mem_valid
|
2012-10-09 22:05:56 +02:00
|
|
|
|
2012-10-23 12:31:34 +02:00
|
|
|
io.out_mem_valid := uncore.io.mem_backup.req.valid
|
|
|
|
uncore.io.mem_backup.req.ready := io.out_mem_ready
|
2012-10-09 22:05:56 +02:00
|
|
|
|
|
|
|
io.mem_backup_en <> uncore.io.mem_backup_en
|
|
|
|
io.mem <> uncore.io.mem
|
|
|
|
}
|