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rocket-chip/src/main/scala/RocketChip.scala

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Scala
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package ReferenceChip
import Chisel._
import Node._
import uncore._
import rocket._
import ReferenceChipBackend._
import scala.collection.mutable.ArrayBuffer
import scala.collection.mutable.HashMap
object ReferenceChipBackend {
val initMap = new HashMap[Component, Bool]()
}
class ReferenceChipBackend extends VerilogBackend
{
override def emitPortDef(m: MemAccess, idx: Int) = {
val res = new StringBuilder()
for (node <- m.mem.inputs) {
if(node.name.contains("init"))
res.append(" .init(" + node.name + "),\n")
}
(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
}
def addMemPin(c: Component) = {
for (node <- Component.nodes) {
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if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
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val init = Bool(INPUT)
init.setName("init")
node.inputs += init
connectMemPin(c, node.component, init)
}
}
}
def connectMemPin(topC: Component, c: Component, p: Bool): Unit = {
p.component = c
var isNewPin = false
val compInitPin =
if (initMap.contains(c)) {
initMap(c)
} else {
isNewPin = true
Bool(INPUT)
}
p.inputs += compInitPin
if (isNewPin) {
compInitPin.setName("init")
c.io.asInstanceOf[Bundle] += compInitPin
initMap += (c -> compInitPin)
connectMemPin(topC, c.parent, compInitPin)
}
}
def addTopLevelPin(c: Component) = {
val init = Bool(INPUT)
init.setName("init")
init.component = c
c.io.asInstanceOf[Bundle] += init
initMap += (c -> init)
}
transforms += ((c: Component) => addTopLevelPin(c))
transforms += ((c: Component) => addMemPin(c))
}
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class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Component
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{
val io = new Bundle {
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val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
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val htif = new ioTileLink().flip
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
val mem = new ioMemPipe
}
import rocket.Constants._
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val hub = new CoherenceHubBroadcast()(conf.copy(ntiles = conf.ntiles+1))
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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val mem_serdes = new MemSerdes(htif_width)
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for (i <- 0 until conf.ntiles) {
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hub.io.tiles(i) <> io.tiles(i)
}
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hub.io.tiles(conf.ntiles) <> io.htif
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
hub.io.mem.resp <> llc.io.cpu.resp
// mux between main and backup memory ports
val mem_cmdq = (new Queue(2)) { new MemReqCmd }
mem_cmdq.io.enq <> llc.io.mem.req_cmd
mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
val mem_dataq = (new Queue(REFILL_CYCLES)) { new MemData }
mem_dataq.io.enq <> llc.io.mem.req_data
mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
io.mem.req_data.bits := mem_dataq.io.deq.bits
mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
io.mem_backup <> mem_serdes.io.narrow
}
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class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Component
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{
val io = new Bundle {
val debug = new ioDebug()
val host = new ioHost(htif_width)
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
val mem = new ioMemPipe
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val tiles = Vec(conf.ntiles) { new ioTileLink() }.flip
val htif = Vec(conf.ntiles) { new ioHTIF(conf.ntiles) }.flip
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}
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val htif = new rocketHTIF(htif_width)
htif.io.cpu <> io.htif
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val outmemsys = new OuterMemorySystem(htif_width)
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outmemsys.io.tiles <> io.tiles
outmemsys.io.htif <> htif.io.mem
io.mem <> outmemsys.io.mem
outmemsys.io.mem_backup_en <> io.mem_backup_en
// pad out the HTIF using a divided clock
val hio = (new slowIO(8)) { Bits(width = htif_width+1) }
hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
htif.io.host.out.ready := hio.io.out_fast.ready
outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
io.host.out.bits := hio.io.out_slow.bits
io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
io.host.in.ready := hio.io.in_slow.ready
outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
htif.io.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
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io.host.clk := hio.io.clk_slow
io.host.clk_edge := Reg(io.host.clk && !Reg(io.host.clk))
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}
class ioTop(htif_width: Int) extends Bundle {
val debug = new rocket.ioDebug();
val host = new rocket.ioHost(htif_width);
val mem_backup_en = Bool(INPUT)
val in_mem_rdy = Bool(OUTPUT)
val in_mem_val = Bool(INPUT)
val out_mem_rdy = Bool(INPUT)
val out_mem_val = Bool(OUTPUT)
val mem = new uncore.ioMem
}
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object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
val NTILES = 1
val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
}
import DummyTopLevelConstants._
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class MemDessert extends Component {
val io = new MemDesserIO(HTIF_WIDTH)
val x = new MemDesser(HTIF_WIDTH)
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}
class Top extends Component {
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val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence
} else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence
}
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implicit val uconf = UncoreConfiguration(NTILES, log2Up(NTILES)+1, co)
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val io = new ioTop(HTIF_WIDTH)
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val uncore = new Uncore(HTIF_WIDTH)
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var error_mode = Bool(false)
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for (i <- 0 until uconf.ntiles) {
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val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
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implicit val rconf = RocketConfiguration(NTILES, co)
val tile = new Tile(resetSignal = hl.reset)
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tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
tl.xact_init <> Queue(tile.io.tilelink.xact_init)
tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data)
tile.io.tilelink.xact_abort <> Queue(tl.xact_abort)
tile.io.tilelink.xact_rep <> Queue(tl.xact_rep, 1, pipe = true)
tl.xact_finish <> Queue(tile.io.tilelink.xact_finish)
tile.io.tilelink.probe_req <> Queue(tl.probe_req)
tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
tl.incoherent := hl.reset
}
io.host <> uncore.io.host
uncore.io.mem_backup.resp.valid := io.in_mem_val
io.out_mem_val := uncore.io.mem_backup.req.valid
uncore.io.mem_backup.req.ready := io.out_mem_rdy
io.mem_backup_en <> uncore.io.mem_backup_en
io.mem <> uncore.io.mem
io.debug.error_mode := error_mode
}