1
0
rocket-chip/src/main/scala/RocketChip.scala

291 lines
11 KiB
Scala
Raw Normal View History

package referencechip
2012-10-09 22:05:56 +02:00
import Chisel._
import uncore._
import rocket._
import rocket.Util._
2012-10-09 22:05:56 +02:00
import ReferenceChipBackend._
import scala.collection.mutable.ArrayBuffer
import scala.collection.mutable.HashMap
object DummyTopLevelConstants {
2013-08-12 19:46:22 +02:00
val NTILES = 1
val NBANKS = 1
val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
2013-08-13 05:52:55 +02:00
val HAS_VEC = false
2013-08-12 19:46:22 +02:00
val HAS_FPU = true
val NL2_REL_XACTS = 1
2013-08-24 22:20:38 +02:00
val NL2_ACQ_XACTS = 7
val NMSHRS = 2
}
2013-08-24 22:20:38 +02:00
import DummyTopLevelConstants._
2012-10-09 22:05:56 +02:00
object ReferenceChipBackend {
2013-08-12 19:46:22 +02:00
val initMap = new HashMap[Module, Bool]()
2012-10-09 22:05:56 +02:00
}
class ReferenceChipBackend extends VerilogBackend
{
override def emitPortDef(m: MemAccess, idx: Int) = {
val res = new StringBuilder()
for (node <- m.mem.inputs) {
if(node.name.contains("init"))
res.append(" .init(" + node.name + "),\n")
}
(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
}
2013-08-12 19:46:22 +02:00
def addMemPin(c: Module) = {
for (node <- Module.nodes) {
2012-10-19 02:51:41 +02:00
if (node.isInstanceOf[Mem[ _ ]] && node.component != null && node.asInstanceOf[Mem[_]].seqRead) {
2013-04-20 10:36:32 +02:00
connectMemPin(c, node.component, node)
2012-10-09 22:05:56 +02:00
}
}
}
2013-08-12 19:46:22 +02:00
def connectMemPin(topC: Module, c: Module, p: Node): Unit = {
2012-10-09 22:05:56 +02:00
var isNewPin = false
val compInitPin =
if (initMap.contains(c)) {
initMap(c)
} else {
isNewPin = true
Bool(INPUT)
}
p.inputs += compInitPin
if (isNewPin) {
compInitPin.setName("init")
c.io.asInstanceOf[Bundle] += compInitPin
2013-04-20 09:38:01 +02:00
compInitPin.component = c
2012-10-09 22:05:56 +02:00
initMap += (c -> compInitPin)
connectMemPin(topC, c.parent, compInitPin)
}
}
2013-08-12 19:46:22 +02:00
def addTopLevelPin(c: Module) = {
2012-10-09 22:05:56 +02:00
val init = Bool(INPUT)
init.setName("init")
init.component = c
c.io.asInstanceOf[Bundle] += init
initMap += (c -> init)
}
2013-08-12 19:46:22 +02:00
transforms += ((c: Module) => addTopLevelPin(c))
transforms += ((c: Module) => addMemPin(c))
2012-10-09 22:05:56 +02:00
}
2013-08-12 19:46:22 +02:00
class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
2012-10-09 22:05:56 +02:00
{
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
2012-10-09 22:05:56 +02:00
val io = new Bundle {
2013-08-12 19:46:22 +02:00
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val htif = (new TileLinkIO).flip
2013-08-12 19:46:22 +02:00
val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
val mem = new ioMem
2012-10-19 02:51:41 +02:00
val mem_backup = new ioMemSerialized(htif_width)
2012-10-09 22:05:56 +02:00
val mem_backup_en = Bool(INPUT)
}
2013-08-12 19:46:22 +02:00
val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
2013-08-12 19:46:22 +02:00
val mem_serdes = Module(new MemSerdes(htif_width))
2012-10-09 22:05:56 +02:00
require(clientEndpoints.length == ln.nClients)
2013-08-12 19:46:22 +02:00
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints))
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
2013-08-12 19:46:22 +02:00
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
if(ln.nMasters > 1) {
2013-08-12 19:46:22 +02:00
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {
conv.io.uncached <> masterEndpoints.head.io.master
2012-10-09 22:05:56 +02:00
}
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, REFILL_CYCLES)
conv.io.mem.resp <> llc.io.cpu.resp
2012-10-09 22:05:56 +02:00
// mux between main and backup memory ports
2013-08-12 19:46:22 +02:00
val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
2012-10-09 22:05:56 +02:00
mem_cmdq.io.enq <> llc.io.mem.req_cmd
mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
2013-08-12 19:46:22 +02:00
val mem_dataq = Module(new Queue(new MemData, REFILL_CYCLES))
2012-10-09 22:05:56 +02:00
mem_dataq.io.enq <> llc.io.mem.req_data
mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
io.mem.req_data.bits := mem_dataq.io.deq.bits
mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
io.mem.resp.ready := Bool(true)
2012-10-09 22:05:56 +02:00
llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
io.mem_backup <> mem_serdes.io.narrow
}
2013-08-25 00:47:42 +02:00
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
2013-08-12 19:46:22 +02:00
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
2012-10-09 22:05:56 +02:00
{
implicit val tl = conf.tl
2012-10-09 22:05:56 +02:00
val io = new Bundle {
val debug = new DebugIO()
val host = new HostIO(htif_width)
val mem = new ioMem
2013-08-12 19:46:22 +02:00
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
2012-10-19 02:51:41 +02:00
val mem_backup = new ioMemSerialized(htif_width)
2012-10-09 22:05:56 +02:00
val mem_backup_en = Bool(INPUT)
}
val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
2013-08-12 19:46:22 +02:00
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
2012-10-19 02:51:41 +02:00
htif.io.cpu <> io.htif
outmemsys.io.mem <> io.mem
2012-10-09 22:05:56 +02:00
outmemsys.io.mem_backup_en <> io.mem_backup_en
// Add networking headers and endpoint queues
2013-08-12 19:46:22 +02:00
def convertAddrToBank(addr: Bits): UInt = {
require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
2013-04-23 02:38:13 +02:00
}
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) =>
outer.acquire <> TileLinkHeaderAppender(client.acquire, i, conf.nBanks, convertAddrToBank _)
outer.release <> TileLinkHeaderAppender(client.release, i, conf.nBanks, convertAddrToBank _)
val grant_ack_q = Queue(client.grant_ack)
outer.grant_ack.valid := grant_ack_q.valid
outer.grant_ack.bits := grant_ack_q.bits
2013-08-12 19:46:22 +02:00
outer.grant_ack.bits.header.src := UInt(i)
grant_ack_q.ready := outer.grant_ack.ready
client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe)
}
2012-10-09 22:05:56 +02:00
// pad out the HTIF using a divided clock
2013-08-12 19:46:22 +02:00
val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) })
hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
hio.io.set_divisor.bits := htif.io.scr.wdata
htif.io.scr.rdata(63) := hio.io.divisor
2012-10-09 22:05:56 +02:00
hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
htif.io.host.out.ready := hio.io.out_fast.ready
outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
io.host.out.bits := hio.io.out_slow.bits
io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
io.host.in.ready := hio.io.in_slow.ready
outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
htif.io.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
2012-10-19 02:51:41 +02:00
io.host.clk := hio.io.clk_slow
2013-08-16 01:37:58 +02:00
io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
2012-10-09 22:05:56 +02:00
}
class TopIO(htifWidth: Int) extends Bundle {
val debug = new DebugIO
val host = new HostIO(htifWidth)
val mem = new ioMem
}
class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
2012-10-09 22:05:56 +02:00
val mem_backup_en = Bool(INPUT)
val in_mem_ready = Bool(OUTPUT)
val in_mem_valid = Bool(INPUT)
val out_mem_ready = Bool(INPUT)
val out_mem_valid = Bool(OUTPUT)
2012-10-09 22:05:56 +02:00
}
2013-08-12 19:46:22 +02:00
class MemDessert extends Module {
2012-10-19 02:51:41 +02:00
val io = new MemDesserIO(HTIF_WIDTH)
2013-08-12 19:46:22 +02:00
val x = Module(new MemDesser(HTIF_WIDTH))
2012-10-19 02:51:41 +02:00
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}
2013-08-12 19:46:22 +02:00
class Top extends Module {
2012-10-09 22:05:56 +02:00
val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence
} else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence
}
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
2013-08-25 00:47:42 +02:00
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
2012-10-19 02:51:41 +02:00
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
2013-08-12 19:46:22 +02:00
fpu = HAS_FPU, vec = HAS_VEC)
val io = new VLSITopIO(HTIF_WIDTH)
2013-08-12 19:46:22 +02:00
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
2013-08-12 19:46:22 +02:00
val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
2012-10-09 22:05:56 +02:00
var error_mode = Bool(false)
for (i <- 0 until uc.nTiles) {
2012-10-09 22:05:56 +02:00
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)
2012-10-19 02:51:41 +02:00
2012-12-13 01:41:21 +01:00
resetSigs(i) := hl.reset
val tile = tileList(i)
tile.io.tilelink <> tl
il := hl.reset
2013-08-16 01:37:58 +02:00
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
2012-10-09 22:05:56 +02:00
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
2013-08-16 01:37:58 +02:00
error_mode = error_mode || Reg(next=tile.io.host.debug.error_mode)
2012-10-09 22:05:56 +02:00
}
io.host <> uncore.io.host
uncore.io.mem_backup.resp.valid := io.in_mem_valid
2012-10-09 22:05:56 +02:00
io.out_mem_valid := uncore.io.mem_backup.req.valid
uncore.io.mem_backup.req.ready := io.out_mem_ready
2012-10-09 22:05:56 +02:00
io.mem_backup_en <> uncore.io.mem_backup_en
io.mem <> uncore.io.mem
io.debug.error_mode := error_mode
}