2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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2011-11-09 23:52:17 +01:00
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import Chisel._;
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2011-10-26 08:02:47 +02:00
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import Node._;
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2011-11-09 23:52:17 +01:00
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import Constants._;
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2011-10-26 08:02:47 +02:00
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import scala.math._;
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2011-11-10 06:54:11 +01:00
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// interface between I$ and pipeline/ITLB (32 bits wide)
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2011-10-26 08:02:47 +02:00
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class ioImem(view: List[String] = null) extends Bundle (view)
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{
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2012-01-18 19:28:48 +01:00
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val invalidate = Bool(INPUT);
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val itlb_miss = Bool(INPUT);
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val req_val = Bool(INPUT);
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val req_idx = Bits(PGIDX_BITS, INPUT);
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val req_ppn = Bits(PPN_BITS, INPUT);
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val resp_data = Bits(32, OUTPUT);
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val resp_val = Bool(OUTPUT);
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2011-10-26 08:02:47 +02:00
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}
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2012-02-07 23:07:42 +01:00
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class ioRocketICache extends Bundle()
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2011-11-05 04:52:21 +01:00
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{
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2011-10-26 08:02:47 +02:00
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val cpu = new ioImem();
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2012-02-29 12:08:04 +01:00
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val mem = new ioTileLink
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2011-10-26 08:02:47 +02:00
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}
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// basic direct mapped instruction cache
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2011-11-10 09:50:09 +01:00
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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2011-10-26 08:02:47 +02:00
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// parameters :
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// lines = # cache lines
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2012-01-25 01:51:30 +01:00
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class rocketICache(sets: Int, assoc: Int) extends Component {
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2012-02-07 23:07:42 +01:00
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val io = new ioRocketICache();
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2011-11-07 09:58:25 +01:00
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2012-01-25 01:51:30 +01:00
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val lines = sets * assoc;
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2011-11-09 23:52:17 +01:00
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val addrbits = PADDR_BITS;
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2012-01-25 01:51:30 +01:00
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val indexbits = log2up(sets);
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2011-12-12 15:49:16 +01:00
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val offsetbits = OFFSET_BITS;
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2011-10-26 08:02:47 +02:00
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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2011-11-12 09:25:06 +01:00
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val tagbits = addrbits-taglsb;
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2011-10-26 08:02:47 +02:00
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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2011-11-07 09:58:25 +01:00
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val databits = 32;
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2012-01-25 00:13:49 +01:00
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val offsetlsb = log2up(databits/8);
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val rf_cnt_bits = log2up(REFILL_CYCLES);
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require(PGIDX_BITS >= taglsb); // virtually-indexed, physically-tagged constraint
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2012-01-25 01:51:30 +01:00
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require(ispow2(sets) && ispow2(assoc));
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2011-10-26 08:02:47 +02:00
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2012-01-12 03:27:11 +01:00
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
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2011-10-26 08:02:47 +02:00
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val state = Reg(resetVal = s_reset);
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2012-01-25 01:51:30 +01:00
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val r_cpu_req_idx = Reg { Bits() }
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val r_cpu_req_ppn = Reg { Bits() }
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2011-11-12 09:25:06 +01:00
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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2012-01-12 04:20:20 +01:00
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val rdy = Wire() { Bool() }
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2012-01-25 01:51:30 +01:00
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val tag_hit = Wire() { Bool() }
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2011-10-26 08:02:47 +02:00
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2012-01-12 04:20:20 +01:00
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when (io.cpu.req_val && rdy) {
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2012-02-12 02:20:33 +01:00
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r_cpu_req_val := Bool(true)
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r_cpu_req_idx := io.cpu.req_idx
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2011-11-05 04:52:21 +01:00
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}
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2012-02-12 02:20:33 +01:00
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.otherwise {
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r_cpu_req_val := Bool(false)
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2011-11-05 04:52:21 +01:00
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}
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2012-01-25 00:13:49 +01:00
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when (state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss) {
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2012-02-12 02:20:33 +01:00
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r_cpu_req_ppn := io.cpu.req_ppn
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2012-01-25 00:13:49 +01:00
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}
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val r_cpu_hit_addr = Cat(io.cpu.req_ppn, r_cpu_req_idx)
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val r_cpu_hit_tag = r_cpu_hit_addr(tagmsb,taglsb)
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val r_cpu_miss_addr = Cat(r_cpu_req_ppn, r_cpu_req_idx)
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val r_cpu_miss_tag = r_cpu_miss_addr(tagmsb,taglsb)
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2011-10-26 08:02:47 +02:00
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2011-11-13 07:13:29 +01:00
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// refill counter
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2011-12-09 09:42:43 +01:00
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
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2012-02-29 12:08:04 +01:00
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when (io.mem.xact_rep.valid) {
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2012-02-12 02:20:33 +01:00
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refill_count := refill_count + UFix(1);
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2011-11-05 04:52:21 +01:00
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}
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2012-01-25 01:51:30 +01:00
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val repl_way = LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0)
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val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
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2011-11-12 09:25:06 +01:00
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val tag_addr =
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2012-01-25 00:13:49 +01:00
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Mux((state === s_refill_wait), r_cpu_req_idx(indexmsb,indexlsb),
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io.cpu.req_idx(indexmsb,indexlsb)).toUFix;
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2012-02-29 12:08:04 +01:00
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val tag_we = (state === s_refill_wait) && io.mem.xact_rep.valid;
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2011-12-04 04:41:15 +01:00
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val data_addr =
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2012-01-25 00:13:49 +01:00
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count),
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io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix;
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2012-01-25 01:51:30 +01:00
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2012-02-01 22:26:04 +01:00
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val data_mux = (new Mux1H(assoc)){Bits(width = MEM_DATA_BITS)}
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2012-01-25 01:51:30 +01:00
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var any_hit = Bool(false)
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for (i <- 0 until assoc)
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{
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val repl_me = (repl_way === UFix(i))
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2012-02-27 02:51:46 +01:00
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val tag_array = Mem(sets){ r_cpu_miss_tag }
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2012-01-25 01:51:30 +01:00
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tag_array.setReadLatency(1);
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tag_array.setTarget('inst);
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me);
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// valid bit array
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2012-02-27 02:51:46 +01:00
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val vb_array = Reg(resetVal = Bits(0, sets));
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2012-01-25 01:51:30 +01:00
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when (io.cpu.invalidate) {
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2012-02-27 02:51:46 +01:00
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vb_array := Bits(0,sets);
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2012-01-25 01:51:30 +01:00
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}
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2012-02-12 02:20:33 +01:00
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.elsewhen (tag_we && repl_me) {
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vb_array := vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, UFix(1,1));
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2012-01-25 01:51:30 +01:00
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}
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val valid = vb_array(r_cpu_req_idx(indexmsb,indexlsb)).toBool;
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val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
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// data array
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2012-02-29 12:08:04 +01:00
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val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data }
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2012-01-25 01:51:30 +01:00
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data_array.setReadLatency(1);
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data_array.setTarget('inst);
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2012-02-29 12:08:04 +01:00
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val data_out = data_array.rw(data_addr, io.mem.xact_rep.bits.data, io.mem.xact_rep.valid && repl_me)
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2012-01-25 01:51:30 +01:00
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data_mux.io.sel(i) := hit
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data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);
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any_hit = any_hit || hit
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}
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tag_hit := any_hit
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2011-12-04 04:41:15 +01:00
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2011-11-07 09:58:25 +01:00
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// output signals
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2012-01-25 00:13:49 +01:00
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_hit;
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2012-01-25 01:51:30 +01:00
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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2012-02-29 12:08:04 +01:00
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io.mem.xact_init.valid := (state === s_request)
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io.mem.xact_init.bits.t_type := X_READ_UNCACHED
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io.mem.xact_init.bits.has_data := Bool(false)
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io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.xact_init_data.valid := Bool(false)
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2011-10-26 08:02:47 +02:00
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// control state machine
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switch (state) {
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is (s_reset) {
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2012-02-12 02:20:33 +01:00
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state := s_ready;
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2011-10-26 08:02:47 +02:00
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}
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is (s_ready) {
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2011-11-13 00:00:45 +01:00
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when (io.cpu.itlb_miss) {
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2012-02-12 02:20:33 +01:00
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state := s_ready;
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2011-11-13 00:00:45 +01:00
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}
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2012-02-12 02:20:33 +01:00
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.elsewhen (r_cpu_req_val && !tag_hit) {
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state := s_request;
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2011-11-13 00:00:45 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_request)
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{
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2012-02-29 12:08:04 +01:00
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when (io.mem.xact_init.ready) {
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2012-02-12 02:20:33 +01:00
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state := s_refill_wait;
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2011-11-12 09:25:06 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill_wait) {
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2012-02-29 12:08:04 +01:00
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when (io.mem.xact_rep.valid) {
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2012-02-12 02:20:33 +01:00
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state := s_refill;
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2011-11-12 09:25:06 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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is (s_refill) {
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2012-02-29 12:08:04 +01:00
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when (io.mem.xact_rep.valid && refill_count.andR) {
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2012-02-12 02:20:33 +01:00
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state := s_ready;
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2011-11-12 09:25:06 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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2012-02-29 12:08:04 +01:00
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}
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2011-10-26 08:02:47 +02:00
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}
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