  Henry StylesandGitHub
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07b2ae07d2
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Merge pull request #4 from sifive/vc707_2GB
Support both 4G and 1GB DIMM configuration for VC707
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2017-09-08 16:09:18 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Henry StylesandGitHub
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385ffa7d9a
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Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:42:32 -07:00 |
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Henry Styles
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b7ee0ab0f0
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:41:12 -07:00 |
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