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6
.gitmodules
vendored
6
.gitmodules
vendored
@ -4,3 +4,9 @@
|
||||
[submodule "freedom"]
|
||||
path = freedom
|
||||
url = https://git.tiband.de/riscv/freedom.git
|
||||
[submodule "src/terminal"]
|
||||
path = src/terminal
|
||||
url = https://git.tiband.de/riscv/terminal.git
|
||||
[submodule "sd-breakout"]
|
||||
path = sd-breakout
|
||||
url = https://git.tiband.de/riscv/sd-breakout.git
|
||||
|
||||
674
LICENSE
Normal file
674
LICENSE
Normal file
@ -0,0 +1,674 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
To protect your rights, we need to prevent others from denying you
|
||||
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|
||||
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||||
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|
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|
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|
||||
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||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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Some devices are designed to deny users access to install or run
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||||
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|
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|
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|
||||
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|
||||
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||||
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||||
Finally, every program is threatened constantly by software patents.
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|
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||||
The precise terms and conditions for copying, distribution and
|
||||
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|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
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|
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||||
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|
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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||||
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||||
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|
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||||
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|
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|
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|
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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A compilation of a covered work with other separate and independent
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|
||||
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|
||||
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||||
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|
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||||
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||||
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|
||||
You may convey a covered work in object code form under the terms
|
||||
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||||
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|
||||
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||||
|
||||
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|
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|
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
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|
||||
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|
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
|
||||
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||||
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|
||||
|
||||
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|
||||
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|
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
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||||
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||||
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||||
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||||
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||||
|
||||
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|
||||
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|
||||
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||||
|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
|
||||
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|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<https://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<https://www.gnu.org/licenses/why-not-lgpl.html>.
|
||||
169
README.md
Normal file
169
README.md
Normal file
@ -0,0 +1,169 @@
|
||||
# RISC-V Linux-Workstation auf dem ML507
|
||||
|
||||
Dieses Repository enthält die Implementierung einer RISC-V-Workstation
|
||||
für das Xilinx ML507-Entwicklungsboard mit Unterstützung für das Booten
|
||||
von Linux von einer SD-Karte. Die Workstation wurde im Rahmen einer
|
||||
[Masterarbeit] an der Universität Leipzig entwickelt.
|
||||
|
||||
## Kompilieren der RISC-V-Toolchain und des Linux-Bootimage
|
||||
|
||||
Da für die Synthese der Workstation aufgrund der Kompilierung des enthaltenen
|
||||
Bootloaders ebenfalls eine RISC-V-Toolchain nötig ist, wird diese zuerst
|
||||
zusammen mit dem Linux-Bootimage erzeugt.
|
||||
|
||||
```sh
|
||||
cd freedom-u-sdk
|
||||
make
|
||||
```
|
||||
|
||||
Falls dabei bei einem „Bleeding edge“-System wie Arch-Linux Fehler auftreten,
|
||||
können nach Bedarf die im `patches`-Ordner verfügbaren Patches angewendet
|
||||
werden. Weitere Details zum Freedom-SDK finden sich u.a. im
|
||||
[Freedom U500 VC707 FPGA Dev Kit Getting Started Guide].
|
||||
|
||||
Anschließend wird das erzeugte Bootimage auf eine SD-Karte übertragen. Dabei
|
||||
darf kein Partitionslayout vorhanden sein.
|
||||
|
||||
```sh
|
||||
sudo dd if=work/bbl.bin of=/dev/sd-card bs=1M
|
||||
sudo sync
|
||||
```
|
||||
|
||||
Während des Kompilierens wird im Ordner `freedom-u-sdk/toolchain` eine RISC-V
|
||||
GCC-Toolchain erstellt. Der Unterordner `bin` sollte für die folgenden
|
||||
Schritte zur `PATH`-Umgebungsvariablen hinzugefügt werden.
|
||||
|
||||
## Synthese der Workstation für das ML507-Entwicklungsboard
|
||||
|
||||
### Erzeugen des Rocket-SOC
|
||||
|
||||
Zuerst wird der Rocket-SoC ohne das BootROM erzeugt:
|
||||
|
||||
```sh
|
||||
cd freedom
|
||||
make -f Makefile.u500ml507devkit verilog
|
||||
```
|
||||
|
||||
Anschließend muss der dabei generierte DeviceTree
|
||||
`sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.dts`
|
||||
im Ordner `builds/u500ml507devkit` wie folgt angepasst werden:
|
||||
|
||||
1. Der verwendete Systemtakt muss zuerst im `soc`-Abschnitt definiert werden:
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <60000000>;
|
||||
};
|
||||
|
||||
2. Anschließend wird er über `clocks = <&sysclk 0>;` in den `serial` und `spi`
|
||||
Abschnitten referenziert.
|
||||
3. Es muss ein Alias für den UART-Controller im Hauptlevel hinzugefügt werden:
|
||||
aliases {
|
||||
serial0 = &L8;
|
||||
};
|
||||
|
||||
4. Die `dts`-Datei muss mit Hilfe des `dtc`-Programms kompiliert werden. Mit
|
||||
dem Ergebniss sollte die in `builds/u500ml507devkit` vorhandenen `dtb`-
|
||||
Datei überschrieben werden.
|
||||
|
||||
Um diese Schritte zu vereinfachen, enthält der `patches`-Ordner bereits
|
||||
fertig angepasste `dts` und `dtb`-Dateien, mit denen die vorhandenen
|
||||
ersetzt werden können.
|
||||
|
||||
Schließlich wird das noch fehlende BootROM erzeugt, wobei dabei auch
|
||||
der Bootloader kompiliert wird:
|
||||
|
||||
```sh
|
||||
make -f Makefile.u500ml507devkit romgen
|
||||
```
|
||||
|
||||
### Erzeugen des MIG-Speichercontrollers
|
||||
|
||||
Da der von MIG erzeugte Speichercontroller nicht ohne weiteres weitergegeben
|
||||
werden darf, muss er von Hand dem ISE-Projekt hinzugefügt werden. Falls beim
|
||||
öffnen des ISE-Projektes eine Meldung bezüglich fehlender Dateien erscheint,
|
||||
wurde entweder der Rocket-SoC nicht korrekt erzeugt oder nicht alle git-
|
||||
Submodule korrekt geklont.
|
||||
|
||||
1. Rechtsklick auf das Projekt, *New Source…*
|
||||
2. *IP (Core Generator & Architecture Wizard)* auswählen
|
||||
3. Als Dateinamen `ddr2_controller` angeben, *Location* übernehmen
|
||||
4. MIG auswählen (zB über die Suche), *Next*, *Finish* -> MIG startet
|
||||
5. Prüfen, ob der korrekte FPGA ausgewählt ist
|
||||
6. Bei den Ausgabeoptionen nochmals den Namen überprüfen und *Create Design*
|
||||
auswählen
|
||||
7. Es sollten keine PIN-kompatiblen FPGAs oder der PPC440 ausgewählt werden
|
||||
8. `DDR2 SDRAM` als Speichertyp auswählen
|
||||
9. 5000 ps / 200 MHz als Takt, bei *Memory Type* `SODIMMs`, bei *Memory Part*
|
||||
das gewünschte Speichermodul (zB `MT4HTF3264HY-667` auf dem ML507) und bei
|
||||
*Date Width* `64` auswählen; Prüfen, ob *Data Mask* aktiviert ist
|
||||
10. Prüfen, ob als *Burst Length* `4` ausgewählt ist
|
||||
11. Den Haken bei *Use PLL* deaktivieren
|
||||
12. Auf der nächsten Seite muss nichts verändert werden
|
||||
13. Bei der Pin-Auswahl *New Design* auswählen und zwei mal bestätigen
|
||||
14. Die Zusammenfassung sollte wie unten lauten
|
||||
15. Das Memory-Modell über *Decline* nicht erzeugen lassen
|
||||
16. Die PCB-Informationen bestätigen und den Controller generieren
|
||||
|
||||
Anschließend kann die Workstation mit einem Doppelklick auf "Generate
|
||||
Programming File" synthetisiert werden. Der erzeugte FPGA-Bitstream befindet
|
||||
sich im Ordner `project/ise/work` und kann per Impact auf das FPGA geladen
|
||||
werden. Details zum Anschluss der SD-Karte befinden sich im Unterordner
|
||||
`sd-breakout`.
|
||||
|
||||
```text
|
||||
CORE Generator Options:
|
||||
Target Device : xc5vfx70t-ff1136
|
||||
Speed Grade : -1
|
||||
HDL : verilog
|
||||
Synthesis Tool : ISE
|
||||
MIG Output Options:
|
||||
Module Name : ddr2_controller
|
||||
No of Controllers : 1
|
||||
Selected Compatible Device(s) : --
|
||||
PPC440 : --
|
||||
PowerPC440 Block Selection : --
|
||||
FPGA Options:
|
||||
PLL : disabled
|
||||
Debug Signals : Disable
|
||||
System Clock : Single-Ended
|
||||
Limit to 2 Bytes per Bank : disabled
|
||||
Extended FPGA Options:
|
||||
DCI for DQ/DQS : enabled
|
||||
DCI for Address/Control : disabled
|
||||
Class for Address and Control : Class II
|
||||
Controller Options:
|
||||
Memory : DDR2_SDRAM
|
||||
Design Clock Frequency : 5000 ps(200.00 MHz)
|
||||
Memory Type : SODIMMs
|
||||
Memory Part : MT4HTF3264HY-667
|
||||
Equivalent Part(s) : --
|
||||
Data Width : 64
|
||||
Memory Depth : 1
|
||||
ECC : ECC Disabled
|
||||
Data Mask : enabled
|
||||
Memory Options:
|
||||
Burst Length (MR[2:0]) : 4(010)
|
||||
Burst Type (MR[3]) : sequential(0)
|
||||
CAS Latency (MR[6:4]) : 4(100)
|
||||
Output Drive Strength (EMR[1]) : Fullstrength(0)
|
||||
RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
|
||||
Additive Latency (EMR[5:3]) : 0(000)
|
||||
FPGA Options:
|
||||
IODELAY Performance Mode : HIGH
|
||||
```
|
||||
|
||||
## Lizenzen
|
||||
|
||||
Alle Komponenten der Workstation sind, wenn nicht anders gekennzeichnet,
|
||||
unter GPLv3 lizenziert. Der für den FPGA erzeugte Bitstream darf jedoch
|
||||
nicht unter GPLv3 und damit gar nicht weitergegeben werden, da er den
|
||||
MIG-Speichercontroller enthält, dessen Quellcode nur unter ganz bestimmten
|
||||
Bedingungen modifiziert und weitergegeben werden darf.
|
||||
|
||||
Die Freedom-Platform ist unter der GPLv3-kompatiblen Apache2 Lizenz und
|
||||
Rocket außerdem unter der BSD-Lizenz lizenziert. Linux ist ausschließlich
|
||||
unter GPLv2 lizenziert.
|
||||
|
||||
[Masterarbeit]: https://klemens.schoelhorn.eu/abschlussarbeiten/
|
||||
[Freedom U500 VC707 FPGA Dev Kit Getting Started Guide]: https://static.dev.sifive.com/SiFive-U500-vc707-gettingstarted-v0.2.pdf
|
||||
2
freedom
2
freedom
Submodule freedom updated: 2c74ef7f03...552553e526
Submodule freedom-u-sdk updated: 0e61cba991...401f509177
30
patches/buildroot-automake.patch
Normal file
30
patches/buildroot-automake.patch
Normal file
@ -0,0 +1,30 @@
|
||||
From 13f00eb4493c217269b76614759e452d8302955e Mon Sep 17 00:00:00 2001
|
||||
From: Paul Eggert <eggert@cs.ucla.edu>
|
||||
Date: Thu, 31 Mar 2016 16:35:29 -0700
|
||||
Subject: automake: port to Perl 5.22 and later
|
||||
|
||||
Without this change, Perl 5.22 complains "Unescaped left brace in
|
||||
regex is deprecated" and this is planned to become a hard error in
|
||||
Perl 5.26. See:
|
||||
http://search.cpan.org/dist/perl-5.22.0/pod/perldelta.pod#A_literal_%22{%22_should_now_be_escaped_in_a_pattern
|
||||
* bin/automake.in (substitute_ac_subst_variables): Escape left brace.
|
||||
---
|
||||
bin/automake.in | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/bin/automake.in b/bin/automake.in
|
||||
index a3a0aa3..2c8f31e 100644
|
||||
--- a/bin/automake.in
|
||||
+++ b/bin/automake.in
|
||||
@@ -3878,7 +3878,7 @@ sub substitute_ac_subst_variables_worker
|
||||
sub substitute_ac_subst_variables
|
||||
{
|
||||
my ($text) = @_;
|
||||
- $text =~ s/\${([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
|
||||
+ $text =~ s/\$[{]([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
|
||||
return $text;
|
||||
}
|
||||
|
||||
--
|
||||
cgit v1.0-41-gc330
|
||||
|
||||
90
patches/buildroot-e2fsprogs.patch
Normal file
90
patches/buildroot-e2fsprogs.patch
Normal file
@ -0,0 +1,90 @@
|
||||
Date: Fri, 29 Dec 2017 10:19:51 -0800
|
||||
From: Palmer Dabbelt <palmer@...belt.com>
|
||||
To: linux-ext4@...r.kernel.org, tytso@....edu
|
||||
Cc: patches@...ups.riscv.org, Palmer Dabbelt <palmer@...belt.com>
|
||||
Subject: [PATCH v2] Rename copy_file_range to copy_file_chunk
|
||||
|
||||
As of 2.27, glibc will have a copy_file_range library call to wrap the
|
||||
new copy_file_range system call. This conflicts with the function in
|
||||
misc/create_inode.c, which this patch renames _copy_file_range.
|
||||
|
||||
Full disclosure: I found this when building e2fsprogs for RISC-V with a
|
||||
glibc-2.27 prerelease, so it's very possible I screwed something up
|
||||
here. Here's the relevant glibc commit:
|
||||
|
||||
commit bad7a0c81f501fbbcc79af9eaa4b8254441c4a1f
|
||||
Author: Florian Weimer <fweimer@...hat.com>
|
||||
Date: Fri Dec 22 10:55:40 2017 +0100
|
||||
|
||||
copy_file_range: New function to copy file data
|
||||
|
||||
The semantics are based on the Linux system call, but a very close
|
||||
emulation in user space is provided.
|
||||
...
|
||||
diff --git a/posix/unistd.h b/posix/unistd.h
|
||||
index 32b0f4898fd2..65317c79fd39 100644
|
||||
--- a/posix/unistd.h
|
||||
+++ b/posix/unistd.h
|
||||
@@ -1105,7 +1105,12 @@ extern int lockf64 (int __fd, int __cmd, __off64_t __len) __wur;
|
||||
do __result = (long int) (expression); \
|
||||
while (__result == -1L && errno == EINTR); \
|
||||
__result; }))
|
||||
-#endif
|
||||
+
|
||||
+/* Copy LENGTH bytes from INFD to OUTFD. */
|
||||
+ssize_t copy_file_range (int __infd, __off64_t *__pinoff,
|
||||
+ int __outfd, __off64_t *__poutoff,
|
||||
+ size_t __length, unsigned int __flags);
|
||||
+#endif /* __USE_GNU */
|
||||
|
||||
Changes since v1:
|
||||
|
||||
* The new name is now copy_file_chunk instead of _copy_file_range.
|
||||
|
||||
Signed-off-by: Palmer Dabbelt <palmer@...belt.com>
|
||||
---
|
||||
misc/create_inode.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/misc/create_inode.c b/misc/create_inode.c
|
||||
index a07f8328e5f9..51d25f8fb005 100644
|
||||
--- a/misc/create_inode.c
|
||||
+++ b/misc/create_inode.c
|
||||
@@ -398,7 +398,7 @@ static ssize_t my_pread(int fd, void *buf, size_t count, off_t offset)
|
||||
}
|
||||
#endif /* !defined HAVE_PREAD64 && !defined HAVE_PREAD */
|
||||
|
||||
-static errcode_t copy_file_range(ext2_filsys fs, int fd, ext2_file_t e2_file,
|
||||
+static errcode_t copy_file_chunk(ext2_filsys fs, int fd, ext2_file_t e2_file,
|
||||
off_t start, off_t end, char *buf,
|
||||
char *zerobuf)
|
||||
{
|
||||
@@ -472,7 +472,7 @@ static errcode_t try_lseek_copy(ext2_filsys fs, int fd, struct stat *statbuf,
|
||||
|
||||
data_blk = data & ~(fs->blocksize - 1);
|
||||
hole_blk = (hole + (fs->blocksize - 1)) & ~(fs->blocksize - 1);
|
||||
- err = copy_file_range(fs, fd, e2_file, data_blk, hole_blk, buf,
|
||||
+ err = copy_file_chunk(fs, fd, e2_file, data_blk, hole_blk, buf,
|
||||
zerobuf);
|
||||
if (err)
|
||||
return err;
|
||||
@@ -523,7 +523,7 @@ static errcode_t try_fiemap_copy(ext2_filsys fs, int fd, ext2_file_t e2_file,
|
||||
goto out;
|
||||
for (i = 0, ext = ext_buf; i < fiemap_buf->fm_mapped_extents;
|
||||
i++, ext++) {
|
||||
- err = copy_file_range(fs, fd, e2_file, ext->fe_logical,
|
||||
+ err = copy_file_chunk(fs, fd, e2_file, ext->fe_logical,
|
||||
ext->fe_logical + ext->fe_length,
|
||||
buf, zerobuf);
|
||||
if (err)
|
||||
@@ -576,7 +576,7 @@ static errcode_t copy_file(ext2_filsys fs, int fd, struct stat *statbuf,
|
||||
goto out;
|
||||
#endif
|
||||
|
||||
- err = copy_file_range(fs, fd, e2_file, 0, statbuf->st_size, buf,
|
||||
+ err = copy_file_chunk(fs, fd, e2_file, 0, statbuf->st_size, buf,
|
||||
zerobuf);
|
||||
out:
|
||||
ext2fs_free_mem(&zerobuf);
|
||||
--
|
||||
2.13.6
|
||||
31
patches/buildroot-libtirpc.patch
Normal file
31
patches/buildroot-libtirpc.patch
Normal file
@ -0,0 +1,31 @@
|
||||
From 1521836c4e0d173767d7417fcc2682cb19ca8aba Mon Sep 17 00:00:00 2001
|
||||
From: Dagg Stompler <daggs@gmx.com>
|
||||
Date: Fri, 29 Dec 2017 15:03:33 +0200
|
||||
Subject: [PATCH] libtirpc: fix compilation error of rpcgen
|
||||
|
||||
When compiling libtirpc, without RPC support available on the host
|
||||
machine, the build of the rpcgen host program because it cannot find
|
||||
the netconfig.h and rpc/types.h headers. Instead of relying on the
|
||||
system-provided ones, let's use the ones included in the libtirpc
|
||||
source code by patching the rpcgen build logic.
|
||||
|
||||
Signed-off-by: Dagg Stompler <daggs@gmx.com>
|
||||
[Thomas: reword commit log.]
|
||||
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
---
|
||||
package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch b/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
|
||||
index 1cf861417c..f2b15fe2f1 100644
|
||||
--- a/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
|
||||
+++ b/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
|
||||
@@ -83,7 +83,7 @@ index 0000000..2277b6f
|
||||
--- /dev/null
|
||||
+++ b/rpcgen/Makefile.am
|
||||
@@ -0,0 +1,22 @@
|
||||
-+COMPILE = $(CC_FOR_BUILD) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
|
||||
++COMPILE = $(CC_FOR_BUILD) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) -I../tirpc $(AM_CPPFLAGS) \
|
||||
+ $(CPPFLAGS_FOR_BUILD) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD)
|
||||
+LINK = $(CC_FOR_BUILD) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(AM_LDFLAGS) $(LDFLAGS_FOR_BUILD) -o $@
|
||||
+
|
||||
26
patches/riscv-binutils-gdb.patch
Normal file
26
patches/riscv-binutils-gdb.patch
Normal file
@ -0,0 +1,26 @@
|
||||
diff --git a/gdb/configure b/gdb/configure
|
||||
index 6a0664ab16..0d1dd0b2b6 100755
|
||||
--- a/gdb/configure
|
||||
+++ b/gdb/configure
|
||||
@@ -10362,7 +10362,7 @@ fi
|
||||
|
||||
|
||||
|
||||
-try_guile_versions="guile-2.2 guile-2.0"
|
||||
+try_guile_versions="guile-2.0"
|
||||
have_libguile=no
|
||||
case "${with_guile}" in
|
||||
no)
|
||||
diff --git a/gdb/configure.ac b/gdb/configure.ac
|
||||
index 10d2d10b12..70a9292e53 100644
|
||||
--- a/gdb/configure.ac
|
||||
+++ b/gdb/configure.ac
|
||||
@@ -1134,7 +1134,7 @@ AC_MSG_RESULT([$with_guile])
|
||||
dnl We check guile with pkg-config.
|
||||
AC_PATH_PROG(pkg_config_prog_path, pkg-config, missing)
|
||||
|
||||
-try_guile_versions="guile-2.2 guile-2.0"
|
||||
+try_guile_versions="guile-2.0"
|
||||
have_libguile=no
|
||||
case "${with_guile}" in
|
||||
no)
|
||||
Binary file not shown.
@ -0,0 +1,128 @@
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "freechips,rocketchip-unknown-dev";
|
||||
model = "freechips,rocketchip-unknown";
|
||||
aliases {
|
||||
serial0 = &L8;
|
||||
};
|
||||
L15: cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
L5: cpu@0 {
|
||||
clock-frequency = <60000000>;
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <64>;
|
||||
d-cache-sets = <64>;
|
||||
d-cache-size = <4096>;
|
||||
d-tlb-sets = <1>;
|
||||
d-tlb-size = <4>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-sets = <64>;
|
||||
i-cache-size = <4096>;
|
||||
i-tlb-sets = <1>;
|
||||
i-tlb-size = <4>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <&L12>;
|
||||
reg = <0>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
status = "okay";
|
||||
timebase-frequency = <1000000>;
|
||||
tlb-split;
|
||||
L3: interrupt-controller {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
};
|
||||
L12: memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
L14: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
|
||||
ranges;
|
||||
sysclk: sysclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <60000000>;
|
||||
};
|
||||
L1: clint@2000000 {
|
||||
compatible = "riscv,clint0";
|
||||
interrupts-extended = <&L3 3 &L3 7>;
|
||||
reg = <0x2000000 0x10000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
L2: debug-controller@0 {
|
||||
compatible = "sifive,debug-013", "riscv,debug-013";
|
||||
interrupts-extended = <&L3 65535>;
|
||||
reg = <0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
L7: error-device@3000 {
|
||||
compatible = "sifive,error0";
|
||||
reg = <0x3000 0x1000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L11: gpio@64002000 {
|
||||
compatible = "sifive,gpio0";
|
||||
interrupt-parent = <&L0>;
|
||||
interrupts = <3 4 5 6 7 8 9 10>;
|
||||
reg = <0x64002000 0x1000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
L0: interrupt-controller@c000000 {
|
||||
#interrupt-cells = <1>;
|
||||
compatible = "riscv,plic0";
|
||||
interrupt-controller;
|
||||
interrupts-extended = <&L3 11 &L3 9>;
|
||||
reg = <0xc000000 0x4000000>;
|
||||
reg-names = "control";
|
||||
riscv,max-priority = <7>;
|
||||
riscv,ndev = <10>;
|
||||
};
|
||||
L6: rom@10000 {
|
||||
compatible = "sifive,maskrom0";
|
||||
reg = <0x10000 0x2000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
L8: serial@64000000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <&L0>;
|
||||
interrupts = <1>;
|
||||
reg = <0x64000000 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&sysclk 0>;
|
||||
};
|
||||
L10: spi@64001000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <&L0>;
|
||||
interrupts = <2>;
|
||||
reg = <0x64001000 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&sysclk 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0x0>;
|
||||
spi-max-frequency = <0x1312d00>;
|
||||
voltage-ranges = <0xce4 0xce4>;
|
||||
disable-wp;
|
||||
};
|
||||
};
|
||||
L9: serial@64003000 {
|
||||
compatible = "klemens,terminal0";
|
||||
reg = <0x64003000 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&sysclk 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
78
project/ise/.gitignore
vendored
Normal file
78
project/ise/.gitignore
vendored
Normal file
@ -0,0 +1,78 @@
|
||||
# intermediate build files
|
||||
*.bgn
|
||||
*.bit
|
||||
*.bld
|
||||
*.cmd_log
|
||||
*.drc
|
||||
*.ll
|
||||
*.lso
|
||||
*.msd
|
||||
*.msk
|
||||
*.ncd
|
||||
*.ngc
|
||||
*.ngd
|
||||
*.ngr
|
||||
*.pad
|
||||
*.par
|
||||
*.pcf
|
||||
*.prj
|
||||
*.ptwx
|
||||
*.rbb
|
||||
*.rbd
|
||||
*.stx
|
||||
*.syr
|
||||
*.twr
|
||||
*.twx
|
||||
*.unroutes
|
||||
*.ut
|
||||
*.xpi
|
||||
*.xst
|
||||
*_bitgen.xwbt
|
||||
*_envsettings.html
|
||||
*_map.map
|
||||
*_map.mrp
|
||||
*_map.ngm
|
||||
*_map.xrpt
|
||||
*_ngdbuild.xrpt
|
||||
*_pad.csv
|
||||
*_pad.txt
|
||||
*_par.xrpt
|
||||
*_summary.html
|
||||
*_summary.xml
|
||||
*_usage.xml
|
||||
*_xst.xrpt
|
||||
|
||||
# iMPACT generated files
|
||||
_impactbatch.log
|
||||
impact.xsl
|
||||
impact_impact.xwbt
|
||||
ise_impact.cmd
|
||||
webtalk_impact.xml
|
||||
|
||||
# Core Generator generated files
|
||||
xaw2verilog.log
|
||||
|
||||
# project-wide generated files
|
||||
*.gise
|
||||
par_usage_statistics.html
|
||||
usage_statistics_webtalk.html
|
||||
webtalk.log
|
||||
webtalk_pn.xml
|
||||
|
||||
# generated folders
|
||||
iseconfig/
|
||||
xlnx_auto_0_xdb/
|
||||
xst/
|
||||
_ngo/
|
||||
_xmsgs/
|
||||
/ipcore_dir/
|
||||
|
||||
# isim
|
||||
/isim*
|
||||
/fuse*
|
||||
*.exe
|
||||
*.wdb
|
||||
xilinxsim.ini
|
||||
|
||||
# log files
|
||||
*.log
|
||||
93
project/ise/ml507_ddr2_clock.v
Normal file
93
project/ise/ml507_ddr2_clock.v
Normal file
@ -0,0 +1,93 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version : 14.7
|
||||
// \ \ Application : xaw2verilog
|
||||
// / / Filename : ml507_ddr2_clock.v
|
||||
// /___/ /\ Timestamp : 05/10/2018 01:18:22
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_ddr2_clock.xaw -st ml507_ddr2_clock.v
|
||||
//Design Name: ml507_ddr2_clock
|
||||
//Device: xc5vfx70t-1ff1136
|
||||
//
|
||||
// Module ml507_ddr2_clock
|
||||
// Generated by Xilinx Architecture Wizard
|
||||
// Written for synthesis tool: XST
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ml507_ddr2_clock(CLKIN_N_IN,
|
||||
CLKIN_P_IN,
|
||||
CLKDV_OUT,
|
||||
CLKIN_IBUFGDS_OUT,
|
||||
CLK0_OUT,
|
||||
CLK90_OUT,
|
||||
LOCKED_OUT);
|
||||
|
||||
input CLKIN_N_IN;
|
||||
input CLKIN_P_IN;
|
||||
output CLKDV_OUT;
|
||||
output CLKIN_IBUFGDS_OUT;
|
||||
output CLK0_OUT;
|
||||
output CLK90_OUT;
|
||||
output LOCKED_OUT;
|
||||
|
||||
wire CLKDV_BUF;
|
||||
wire CLKFB_IN;
|
||||
wire CLKIN_IBUFGDS;
|
||||
wire CLK0_BUF;
|
||||
wire CLK90_BUF;
|
||||
wire GND_BIT;
|
||||
wire [6:0] GND_BUS_7;
|
||||
wire [15:0] GND_BUS_16;
|
||||
|
||||
assign GND_BIT = 0;
|
||||
assign GND_BUS_7 = 7'b0000000;
|
||||
assign GND_BUS_16 = 16'b0000000000000000;
|
||||
assign CLKIN_IBUFGDS_OUT = CLKIN_IBUFGDS;
|
||||
assign CLK0_OUT = CLKFB_IN;
|
||||
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
|
||||
.O(CLKDV_OUT));
|
||||
IBUFGDS CLKIN_IBUFGDS_INST (.I(CLKIN_P_IN),
|
||||
.IB(CLKIN_N_IN),
|
||||
.O(CLKIN_IBUFGDS));
|
||||
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
||||
.O(CLKFB_IN));
|
||||
BUFG CLK90_BUFG_INST (.I(CLK90_BUF),
|
||||
.O(CLK90_OUT));
|
||||
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
|
||||
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(5.000),
|
||||
.CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"),
|
||||
.DCM_PERFORMANCE_MODE("MAX_SPEED"),
|
||||
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
|
||||
.DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"),
|
||||
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
|
||||
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
|
||||
.CLKIN(CLKIN_IBUFGDS),
|
||||
.DADDR(GND_BUS_7[6:0]),
|
||||
.DCLK(GND_BIT),
|
||||
.DEN(GND_BIT),
|
||||
.DI(GND_BUS_16[15:0]),
|
||||
.DWE(GND_BIT),
|
||||
.PSCLK(GND_BIT),
|
||||
.PSEN(GND_BIT),
|
||||
.PSINCDEC(GND_BIT),
|
||||
.RST(GND_BIT),
|
||||
.CLKDV(CLKDV_BUF),
|
||||
.CLKFX(),
|
||||
.CLKFX180(),
|
||||
.CLK0(CLK0_BUF),
|
||||
.CLK2X(),
|
||||
.CLK2X180(),
|
||||
.CLK90(CLK90_BUF),
|
||||
.CLK180(),
|
||||
.CLK270(),
|
||||
.DO(),
|
||||
.DRDY(),
|
||||
.LOCKED(LOCKED_OUT),
|
||||
.PSDONE());
|
||||
endmodule
|
||||
81
project/ise/ml507_dvi_clock.v
Normal file
81
project/ise/ml507_dvi_clock.v
Normal file
@ -0,0 +1,81 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version : 14.7
|
||||
// \ \ Application : xaw2verilog
|
||||
// / / Filename : ml507_dvi_clock.v
|
||||
// /___/ /\ Timestamp : 04/30/2018 22:20:54
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_dvi_clock.xaw -st ml507_dvi_clock.v
|
||||
//Design Name: ml507_dvi_clock
|
||||
//Device: xc5vfx70t-1ff1136
|
||||
//
|
||||
// Module ml507_dvi_clock
|
||||
// Generated by Xilinx Architecture Wizard
|
||||
// Written for synthesis tool: XST
|
||||
// Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI
|
||||
// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ml507_dvi_clock(CLKIN_IN,
|
||||
CLKFX_OUT,
|
||||
CLK0_OUT,
|
||||
LOCKED_OUT);
|
||||
|
||||
input CLKIN_IN;
|
||||
output CLKFX_OUT;
|
||||
output CLK0_OUT;
|
||||
output LOCKED_OUT;
|
||||
|
||||
wire CLKFB_IN;
|
||||
wire CLKFX_BUF;
|
||||
wire CLK0_BUF;
|
||||
wire GND_BIT;
|
||||
wire [6:0] GND_BUS_7;
|
||||
wire [15:0] GND_BUS_16;
|
||||
|
||||
assign GND_BIT = 0;
|
||||
assign GND_BUS_7 = 7'b0000000;
|
||||
assign GND_BUS_16 = 16'b0000000000000000;
|
||||
assign CLK0_OUT = CLKFB_IN;
|
||||
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
|
||||
.O(CLKFX_OUT));
|
||||
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
||||
.O(CLKFB_IN));
|
||||
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25),
|
||||
.CLKFX_MULTIPLY(12), .CLKIN_DIVIDE_BY_2("FALSE"),
|
||||
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
|
||||
.DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"),
|
||||
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
|
||||
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
|
||||
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
|
||||
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
|
||||
.CLKIN(CLKIN_IN),
|
||||
.DADDR(GND_BUS_7[6:0]),
|
||||
.DCLK(GND_BIT),
|
||||
.DEN(GND_BIT),
|
||||
.DI(GND_BUS_16[15:0]),
|
||||
.DWE(GND_BIT),
|
||||
.PSCLK(GND_BIT),
|
||||
.PSEN(GND_BIT),
|
||||
.PSINCDEC(GND_BIT),
|
||||
.RST(GND_BIT),
|
||||
.CLKDV(),
|
||||
.CLKFX(CLKFX_BUF),
|
||||
.CLKFX180(),
|
||||
.CLK0(CLK0_BUF),
|
||||
.CLK2X(),
|
||||
.CLK2X180(),
|
||||
.CLK90(),
|
||||
.CLK180(),
|
||||
.CLK270(),
|
||||
.DO(),
|
||||
.DRDY(),
|
||||
.LOCKED(LOCKED_OUT),
|
||||
.PSDONE());
|
||||
endmodule
|
||||
81
project/ise/ml507_sys_clock.v
Normal file
81
project/ise/ml507_sys_clock.v
Normal file
@ -0,0 +1,81 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version : 14.7
|
||||
// \ \ Application : xaw2verilog
|
||||
// / / Filename : ml507_sys_clock.v
|
||||
// /___/ /\ Timestamp : 05/13/2018 21:08:59
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_sys_clock.xaw -st ml507_sys_clock.v
|
||||
//Design Name: ml507_sys_clock
|
||||
//Device: xc5vfx70t-1ff1136
|
||||
//
|
||||
// Module ml507_sys_clock
|
||||
// Generated by Xilinx Architecture Wizard
|
||||
// Written for synthesis tool: XST
|
||||
// Period Jitter (unit interval) for block DCM_ADV_INST = 0.010 UI
|
||||
// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.174 ns
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ml507_sys_clock(CLKIN_IN,
|
||||
CLKFX_OUT,
|
||||
CLK0_OUT,
|
||||
LOCKED_OUT);
|
||||
|
||||
input CLKIN_IN;
|
||||
output CLKFX_OUT;
|
||||
output CLK0_OUT;
|
||||
output LOCKED_OUT;
|
||||
|
||||
wire CLKFB_IN;
|
||||
wire CLKFX_BUF;
|
||||
wire CLK0_BUF;
|
||||
wire GND_BIT;
|
||||
wire [6:0] GND_BUS_7;
|
||||
wire [15:0] GND_BUS_16;
|
||||
|
||||
assign GND_BIT = 0;
|
||||
assign GND_BUS_7 = 7'b0000000;
|
||||
assign GND_BUS_16 = 16'b0000000000000000;
|
||||
assign CLK0_OUT = CLKFB_IN;
|
||||
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
|
||||
.O(CLKFX_OUT));
|
||||
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
||||
.O(CLKFB_IN));
|
||||
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(5),
|
||||
.CLKFX_MULTIPLY(3), .CLKIN_DIVIDE_BY_2("FALSE"),
|
||||
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
|
||||
.DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"),
|
||||
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
|
||||
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
|
||||
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
|
||||
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
|
||||
.CLKIN(CLKIN_IN),
|
||||
.DADDR(GND_BUS_7[6:0]),
|
||||
.DCLK(GND_BIT),
|
||||
.DEN(GND_BIT),
|
||||
.DI(GND_BUS_16[15:0]),
|
||||
.DWE(GND_BIT),
|
||||
.PSCLK(GND_BIT),
|
||||
.PSEN(GND_BIT),
|
||||
.PSINCDEC(GND_BIT),
|
||||
.RST(GND_BIT),
|
||||
.CLKDV(),
|
||||
.CLKFX(CLKFX_BUF),
|
||||
.CLKFX180(),
|
||||
.CLK0(CLK0_BUF),
|
||||
.CLK2X(),
|
||||
.CLK2X180(),
|
||||
.CLK90(),
|
||||
.CLK180(),
|
||||
.CLK270(),
|
||||
.DO(),
|
||||
.DRDY(),
|
||||
.LOCKED(LOCKED_OUT),
|
||||
.PSDONE());
|
||||
endmodule
|
||||
432
project/ise/risc-v-workstation.xise
Normal file
432
project/ise/risc-v-workstation.xise
Normal file
@ -0,0 +1,432 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="../../freedom/builds/u500ml507devkit/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/builds/u500ml507devkit/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.rom.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/rocket-chip/vsrc/AsyncResetReg.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/fpga-shells/xilinx/vc707/vsrc/sdio.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/fpga-shells/xilinx/vc707/vsrc/vc707reset.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/fpga-shells/xilinx/common/vsrc/PowerOnResetFPGAOnly.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/memory_controller.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/terminal.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/vga.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/framebuffer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/ram_2port.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/terminal/i2c_master.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="ml507_ddr2_clock.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="ml507_dvi_clock.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="ml507_sys_clock.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/main.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../src/ddr2.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../freedom/rocket-chip/vsrc/plusarg_reader.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc5vfx70t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|U500ML507DevKitFPGAChip" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../freedom/builds/u500ml507devkit/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/U500ML507DevKitFPGAChip" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="-use_new_parser yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="U500ML507DevKitFPGAChip" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ff1136" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="U500ML507DevKitFPGAChip_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="U500ML507DevKitFPGAChip_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="U500ML507DevKitFPGAChip_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="U500ML507DevKitFPGAChip_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="U500ML507DevKitFPGAChip" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="SYNTHESIS" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="work" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="risc-v-workstation" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-06-05T15:43:22" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8F432ACFFFD0EA75628131A043599093" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
1
sd-breakout
Submodule
1
sd-breakout
Submodule
Submodule sd-breakout added at 2323183979
269
src/ddr2.ucf
Normal file
269
src/ddr2.ucf
Normal file
@ -0,0 +1,269 @@
|
||||
NET ddr2_a[0] LOC="L30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[1] LOC="M30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[2] LOC="N29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[3] LOC="P29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[4] LOC="K31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[5] LOC="L31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[6] LOC="P31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[7] LOC="P30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[8] LOC="M31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[9] LOC="R28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[10] LOC="J31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[11] LOC="R29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_a[12] LOC="T31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr2_a[13] LOC="H29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ba[0] LOC="G31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ba[1] LOC="J30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr2_ba[2] LOC="R31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_cas_n LOC="E31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_cke LOC="T28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ck_n[0] LOC="AJ29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ck[0] LOC="AK29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ck_n[1] LOC="F28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ck[1] LOC="E28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_cs_n LOC="L29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[0] LOC="AF30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[1] LOC="AK31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[2] LOC="AF31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[3] LOC="AD30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[4] LOC="AJ30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[5] LOC="AF29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[6] LOC="AD29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[7] LOC="AE29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[8] LOC="AH27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[9] LOC="AF28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[10] LOC="AH28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[11] LOC="AA28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[12] LOC="AG25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[13] LOC="AJ26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[14] LOC="AG28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[15] LOC="AB28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[16] LOC="AC28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[17] LOC="AB25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[18] LOC="AC27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[19] LOC="AA26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[20] LOC="AB26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[21] LOC="AA24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[22] LOC="AB27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[23] LOC="AA25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[24] LOC="AC29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[25] LOC="AB30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[26] LOC="W31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[27] LOC="V30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[28] LOC="AC30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[29] LOC="W29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[30] LOC="V27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[31] LOC="W27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[32] LOC="V29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[33] LOC="Y27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[34] LOC="Y26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[35] LOC="W24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[36] LOC="V28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[37] LOC="W25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[38] LOC="W26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[39] LOC="V24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[40] LOC="R24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[41] LOC="P25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[42] LOC="N24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[43] LOC="P26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[44] LOC="T24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[45] LOC="N25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[46] LOC="P27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[47] LOC="N28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[48] LOC="M28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[49] LOC="L28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[50] LOC="F25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[51] LOC="H25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[52] LOC="K27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[53] LOC="K28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[54] LOC="H24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[55] LOC="G26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[56] LOC="G25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[57] LOC="M26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[58] LOC="J24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[59] LOC="L26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[60] LOC="J27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[61] LOC="M25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[62] LOC="L25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dq[63] LOC="L24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[0] LOC="AJ31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[1] LOC="AE28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[2] LOC="Y24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[3] LOC="Y31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[4] LOC="V25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[5] LOC="P24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[6] LOC="F26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dm[7] LOC="J25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[0] LOC="AA30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[0] LOC="AA29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[1] LOC="AK27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[1] LOC="AK28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[2] LOC="AJ27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[2] LOC="AK26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[3] LOC="AA31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[3] LOC="AB31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[4] LOC="Y29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[4] LOC="Y28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[5] LOC="E27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[5] LOC="E26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[6] LOC="G28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[6] LOC="H28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs_n[7] LOC="H27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_dqs[7] LOC="G27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_odt LOC="F31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_ras_n LOC="H30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
NET ddr2_we_n LOC="K29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
|
||||
|
||||
NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;
|
||||
NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_we_n" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_cs_n" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_odt" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_cke" IOSTANDARD = SSTL18_II;
|
||||
NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II_DCI;
|
||||
NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
|
||||
|
||||
|
||||
################################################################################
|
||||
# Copied from ddr2_controller #
|
||||
################################################################################
|
||||
|
||||
|
||||
###############################################################################
|
||||
# Define multicycle paths - these paths may take longer because additional
|
||||
# time allowed for logic to settle in calibration/initialization FSM
|
||||
###############################################################################
|
||||
|
||||
# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
|
||||
# multicycle paths from originating flip-flop to ANY destination
|
||||
# flip-flop (or in some cases, it can also be a BRAM)
|
||||
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
|
||||
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
|
||||
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
|
||||
"TS_CLK_200" * 4;
|
||||
# MUX select for read data - optional delay on data to account for byte skews
|
||||
INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
|
||||
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
|
||||
"TS_CLK_200" * 4;
|
||||
# Calibration/Initialization complete status flag (for PHY logic only) - can
|
||||
# be used to drive both flip-flops and BRAMs
|
||||
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
|
||||
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
|
||||
"TS_CLK_200" * 4;
|
||||
# The RAM path is only used in cases where Write Latency (Additive Latency +
|
||||
# (CAS Latency - 1) + (1 in case of RDIMM)) is 2 or below. So these constraints are
|
||||
# valid for CAS Latency = 3, Additive Latency = 0 and selected part is not RDIMM.
|
||||
# If Write Latency is higher than 3, then a warning will appear in PAR,
|
||||
# and the constraint can be ignored as this path does not exist. RAM constraint
|
||||
# can be safely removed if the warning is not to be displayed.
|
||||
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
|
||||
"TS_CLK_200" * 4;
|
||||
# Select (address) bits for SRL32 shift registers used in stage3/stage4
|
||||
# calibration
|
||||
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
|
||||
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_CLK_200" * 4;
|
||||
|
||||
INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
|
||||
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_CLK_200" * 4;
|
||||
|
||||
INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
|
||||
TNM = "TNM_CAL_RDEN_DLY";
|
||||
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
|
||||
"TS_CLK_200" * 4;
|
||||
###############################################################################
|
||||
#The following constraint is added to prevent (false) hold time violations on
|
||||
#the data path from stage1 to stage2 capture flops. Stage1 flops are clocked by
|
||||
#the delayed DQS and stage2 flops are clocked by the clk0 clock. Placing a TIG
|
||||
#on the DQ IDDR capture flop instance to achieve this is acceptable because timing
|
||||
#is guaranteed through the use of separate Predictable IP constraints. These
|
||||
#violations are reported when anunconstrained path report is run.
|
||||
###############################################################################
|
||||
INST "*/gen_dq[*].u_iob_dq/gen*.u_iddr_dq" TIG ;
|
||||
###############################################################################
|
||||
# DQS Read Post amble Glitch Squelch circuit related constraints
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
# LOC placement of DQS-squelch related IDDR and IDELAY elements
|
||||
# Each circuit can be located at any of the following locations:
|
||||
# 1. Unused "N"-side of DQS differential pair I/O
|
||||
# 2. DM data mask (output only, input side is free for use)
|
||||
# 3. Any output-only site
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
#The following constraint is added to avoid the HOLD violations in the trace report
|
||||
#when run for unconstrained paths.These two FF groups will be clocked by two different
|
||||
# clocks and hence there should be no timing analysis performed on this path.
|
||||
###############################################################################
|
||||
INST "*/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[*].u_en_dqs_ff" TNM = EN_DQS_FF;
|
||||
TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;
|
||||
|
||||
INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
|
||||
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
|
||||
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
|
||||
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
|
||||
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
|
||||
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
|
||||
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
|
||||
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
|
||||
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
|
||||
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
|
||||
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
|
||||
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
|
||||
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
|
||||
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
|
||||
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
|
||||
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
|
||||
|
||||
###############################################################################
|
||||
# LOC and timing constraints for flop driving DQS CE enable signal
|
||||
# from fabric logic. Even though the absolute delay on this path is
|
||||
# calibrated out (when synchronizing this output to DQS), the delay
|
||||
# should still be kept as low as possible to reduce post-calibration
|
||||
# voltage/temp variations - these are roughly proportional to the
|
||||
# absolute delay of the path.
|
||||
# The following code has been commented for V5 as the predictable IP will take
|
||||
# care of placement of these flops by meeting the MAXDELAY requirement.
|
||||
# These constraints will be removed in the next release.
|
||||
###############################################################################
|
||||
|
||||
INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
|
||||
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
|
||||
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
|
||||
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
|
||||
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
|
||||
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
|
||||
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
|
||||
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
|
||||
|
||||
# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
|
||||
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
|
||||
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
|
||||
# This can be relaxed by the user for lower frequencies:
|
||||
# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
|
||||
# In general PAR should be able to route this
|
||||
# within 900ps over all speed grades.
|
||||
NET "*/u_phy_io/en_dqs[*]" MAXDELAY = 600 ps;
|
||||
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
|
||||
|
||||
###############################################################################
|
||||
# "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's
|
||||
# for DQS Read Post amble Glitch Squelch circuit
|
||||
###############################################################################
|
||||
|
||||
# Max delay from output of IOB flip-flop to CE input of DQ IDDRs =
|
||||
# tRPST + some slack where slack account for rise-time of DQS on board.
|
||||
# For now assume slack = 0.400ns (based on initial SPICE simulations,
|
||||
# assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
|
||||
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
|
||||
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
|
||||
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 2.4 ns;
|
||||
70
src/main.ucf
Normal file
70
src/main.ucf
Normal file
@ -0,0 +1,70 @@
|
||||
NET "sys_clock" LOC = AH15;
|
||||
NET "sys_clock" PERIOD = 100 MHz HIGH 50%;
|
||||
|
||||
NET "ddr_clock_p" LOC = L19 | DIFF_TERM = TRUE;
|
||||
NET "ddr_clock_n" LOC = K19 | DIFF_TERM = TRUE;
|
||||
NET "ddr_clock_p" TNM_NET = "CLK_200";
|
||||
TIMESPEC "TS_CLK_200" = PERIOD "CLK_200" 5 ns HIGH 50%;
|
||||
# ddr_clock_n period doesn't need to be specified
|
||||
|
||||
NET "reset" LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI, Center
|
||||
|
||||
NET "clock_led" LOC="AG12"; # LED South
|
||||
NET "reset_led" LOC="E8"; # LED Center
|
||||
|
||||
NET "uart_rx" LOC="AG15";
|
||||
NET "uart_tx" LOC="AG20";
|
||||
|
||||
NET "led_0" LOC = H18; # no DCI
|
||||
NET "led_1" LOC = L18; # no DCI
|
||||
NET "led_2" LOC = G15; # no DCI
|
||||
NET "led_3" LOC = AD26 | IOSTANDARD = LVCMOS18;
|
||||
NET "led_4" LOC = G16; # no DCI
|
||||
NET "led_5" LOC = AD25 | IOSTANDARD = LVCMOS18;
|
||||
NET "led_6" LOC = AD24 | IOSTANDARD = LVCMOS18;
|
||||
NET "led_7" LOC = AE24 | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "dip_0" LOC="U25" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_1" LOC="AG27" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_2" LOC="AF25" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_3" LOC="AF26" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_4" LOC="AE27" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_5" LOC="AE26" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_6" LOC="AC25" | IOSTANDARD = LVCMOS18;
|
||||
NET "dip_7" LOC="AC24" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
# HDR1 2–12
|
||||
NET "sdio_clk" LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "sdio_cmd" LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "sdio_dat[3]" LOC="H34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "sdio_dat[2]" LOC="G33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "sdio_dat[1]" LOC="G32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "sdio_dat[0]" LOC="H32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
|
||||
# HDR1 14–20
|
||||
NET "jtag_TCK" LOC="J32" | PULLUP | CLOCK_DEDICATED_ROUTE = FALSE; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "jtag_TMS" LOC="J34" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "jtag_TDI" LOC="L33" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
NET "jtag_TDO" LOC="M32" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
|
||||
|
||||
# Termial DVI
|
||||
NET "dvi_d(0)" LOC = AB8;
|
||||
NET "dvi_d(1)" LOC = AC8;
|
||||
NET "dvi_d(2)" LOC = AN12;
|
||||
NET "dvi_d(3)" LOC = AP12;
|
||||
NET "dvi_d(4)" LOC = AA9;
|
||||
NET "dvi_d(5)" LOC = AA8;
|
||||
NET "dvi_d(6)" LOC = AM13;
|
||||
NET "dvi_d(7)" LOC = AN13;
|
||||
NET "dvi_d(8)" LOC = AA10;
|
||||
NET "dvi_d(9)" LOC = AB10;
|
||||
NET "dvi_d(10)" LOC = AP14;
|
||||
NET "dvi_d(11)" LOC = AN14;
|
||||
NET "dvi_clk_p" LOC = AL11;
|
||||
NET "dvi_clk_n" LOC = AL10;
|
||||
NET "dvi_hsync" LOC = AM12;
|
||||
NET "dvi_vsync" LOC = AM11;
|
||||
NET "dvi_de" LOC = AE8;
|
||||
NET "dvi_reset" LOC = AK6;
|
||||
NET "dvi_i2c_scl" LOC = U27 | IOSTANDARD = LVCMOS18;
|
||||
NET "dvi_i2c_sda" LOC = T29 | IOSTANDARD = LVCMOS18;
|
||||
241
src/memory_controller.vhd
Normal file
241
src/memory_controller.vhd
Normal file
@ -0,0 +1,241 @@
|
||||
library ieee;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity memory_controller is
|
||||
port (
|
||||
-- clocks
|
||||
sys_clk0: in std_logic;
|
||||
sys_clk90: in std_logic;
|
||||
sys_clkdiv0: in std_logic;
|
||||
sys_clk_locked: in std_logic;
|
||||
sys_clk_idelay: in std_logic;
|
||||
sys_reset: in std_logic;
|
||||
|
||||
-- read and write requests
|
||||
request_addr: in std_logic_vector(27 downto 0); -- 256 MiB, no CS (SR)
|
||||
request_type: in std_logic; -- read (1) or write (0)
|
||||
request_data: in std_logic_vector(255 downto 0);
|
||||
request_mask: in std_logic_vector(31 downto 0);
|
||||
request_valid: in std_logic;
|
||||
request_ready: out std_logic;
|
||||
|
||||
-- read responses
|
||||
response_data: out std_logic_vector(255 downto 0);
|
||||
response_valid: out std_logic; -- only asserted for one cycle, no ready
|
||||
|
||||
-- physical ddr2 interface
|
||||
ddr2_dq: inout std_logic_vector(63 downto 0);
|
||||
ddr2_a: out std_logic_vector(12 downto 0);
|
||||
ddr2_ba: out std_logic_vector(1 downto 0);
|
||||
ddr2_ras_n: out std_logic;
|
||||
ddr2_cas_n: out std_logic;
|
||||
ddr2_we_n: out std_logic;
|
||||
ddr2_cs_n: out std_logic_vector(0 downto 0);
|
||||
ddr2_odt: out std_logic_vector(0 downto 0);
|
||||
ddr2_cke: out std_logic_vector(0 downto 0);
|
||||
ddr2_dm: out std_logic_vector(7 downto 0);
|
||||
ddr2_dqs: inout std_logic_vector(7 downto 0);
|
||||
ddr2_dqs_n: inout std_logic_vector(7 downto 0);
|
||||
ddr2_ck: out std_logic_vector(1 downto 0);
|
||||
ddr2_ck_n: out std_logic_vector(1 downto 0)
|
||||
);
|
||||
end memory_controller;
|
||||
|
||||
architecture rtl of memory_controller is
|
||||
|
||||
signal clk: std_logic;
|
||||
signal reset_p: std_logic;
|
||||
|
||||
type request_states is (
|
||||
REQ_IDLE,
|
||||
REQ_WRITE
|
||||
);
|
||||
signal request_state: request_states := REQ_IDLE;
|
||||
|
||||
type response_states is (
|
||||
RES_IDLE,
|
||||
RES_WAIT_SECOND
|
||||
);
|
||||
signal response_state: response_states := RES_IDLE;
|
||||
|
||||
signal ram_init_done: std_logic;
|
||||
|
||||
signal ram_address: std_logic_vector(30 downto 0);
|
||||
signal ram_command: std_logic_vector(2 downto 0);
|
||||
signal ram_data_in: std_logic_vector(127 downto 0);
|
||||
signal ram_mask_in: std_logic_vector(15 downto 0);
|
||||
signal ram_data_out: std_logic_vector(127 downto 0);
|
||||
signal ram_enq_address: std_logic;
|
||||
signal ram_enq_data: std_logic;
|
||||
signal ram_address_afull: std_logic;
|
||||
signal ram_data_afull: std_logic;
|
||||
signal ram_data_valid: std_logic;
|
||||
|
||||
signal is_request_ready: std_logic;
|
||||
|
||||
signal data_in_high: std_logic_vector(127 downto 0);
|
||||
signal mask_in_high: std_logic_vector(15 downto 0);
|
||||
signal data_out_low: std_logic_vector(127 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
reset_p <= not sys_reset;
|
||||
|
||||
-- the lowest three bits pick one of the 8 bytes inside the 64b ram width
|
||||
ram_address <= "000000" & request_addr(27 downto 3);
|
||||
-- WRITE is 000 and READ is 001
|
||||
ram_command <= "00" & request_type;
|
||||
-- we directly pass the lower half to the mig fifo and only store the
|
||||
-- upper half for writing on a second cycle (this works because we can
|
||||
-- still write 12 words to the fifo when the *almost full* signal is
|
||||
-- asserted by the mig)
|
||||
ram_data_in <= request_data(127 downto 0) when request_state = REQ_IDLE else
|
||||
data_in_high;
|
||||
ram_mask_in <= request_mask(15 downto 0) when request_state = REQ_IDLE else
|
||||
mask_in_high;
|
||||
-- to directly pass data to the fifos (see above) we also have to enable
|
||||
-- the fifo write signals combinatorially, otherwise we miss the first part
|
||||
ram_enq_address <= is_request_ready and request_valid;
|
||||
-- the data write signal is only high for write requests and also has to
|
||||
-- be kept high for a second cycle to write the upper half of the data
|
||||
ram_enq_data <= '1' when ( (is_request_ready and request_valid) = '1' and
|
||||
(request_type = '0')
|
||||
) or (request_state = REQ_WRITE)
|
||||
else '0';
|
||||
-- we are only ready if we can write to *both* fifos and everything is
|
||||
-- fully initialized (we could theoretically only look at the address fifo
|
||||
-- for read requests)
|
||||
is_request_ready <= '1' when (ram_init_done = '1') and
|
||||
(ram_address_afull = '0') and
|
||||
(ram_data_afull = '0') and
|
||||
(request_state = REQ_IDLE)
|
||||
else '0';
|
||||
request_ready <= is_request_ready;
|
||||
|
||||
input: process(clk, sys_reset)
|
||||
begin
|
||||
if sys_reset = '1' then
|
||||
request_state <= REQ_IDLE;
|
||||
elsif rising_edge(clk) then
|
||||
case request_state is
|
||||
when REQ_IDLE =>
|
||||
if is_request_ready = '1' and request_valid = '1' then
|
||||
if request_type = '1' then -- READ
|
||||
request_state <= REQ_IDLE;
|
||||
else -- WRITE
|
||||
data_in_high <= request_data(255 downto 128);
|
||||
mask_in_high <= request_mask(31 downto 16);
|
||||
request_state <= REQ_WRITE;
|
||||
end if;
|
||||
end if;
|
||||
when REQ_WRITE =>
|
||||
request_state <= REQ_IDLE;
|
||||
end case;
|
||||
end if;
|
||||
end process input;
|
||||
|
||||
|
||||
-- we pass the higher half directly from the mig
|
||||
response_data <= ram_data_out & data_out_low;
|
||||
-- read_valid only asserted for one cycle, must be read immediately
|
||||
response_valid <= '1' when (response_state = RES_WAIT_SECOND) and
|
||||
(ram_data_valid = '1')
|
||||
else '0';
|
||||
|
||||
output: process(clk, sys_reset)
|
||||
begin
|
||||
if sys_reset = '1' then
|
||||
response_state <= RES_IDLE;
|
||||
elsif rising_edge(clk) then
|
||||
case response_state is
|
||||
when RES_IDLE =>
|
||||
if ram_data_valid = '1' then
|
||||
data_out_low <= ram_data_out;
|
||||
response_state <= RES_WAIT_SECOND;
|
||||
end if;
|
||||
when RES_WAIT_SECOND =>
|
||||
if ram_data_valid = '1' then
|
||||
response_state <= RES_IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end process output;
|
||||
|
||||
ddr2_controller: entity work.ddr2_controller port map (
|
||||
clk0 => sys_clk0,
|
||||
clk90 => sys_clk90,
|
||||
clkdiv0 => sys_clkdiv0,
|
||||
clk200 => sys_clk_idelay,
|
||||
locked => sys_clk_locked,
|
||||
sys_rst_n => reset_p,
|
||||
rst0_tb => open,
|
||||
clk0_tb => clk,
|
||||
phy_init_done => ram_init_done,
|
||||
app_wdf_afull => ram_data_afull,
|
||||
app_af_afull => ram_address_afull,
|
||||
rd_data_valid => ram_data_valid,
|
||||
app_wdf_wren => ram_enq_data,
|
||||
app_af_wren => ram_enq_address,
|
||||
app_af_addr => ram_address,
|
||||
app_af_cmd => ram_command,
|
||||
rd_data_fifo_out => ram_data_out,
|
||||
app_wdf_data => ram_data_in,
|
||||
app_wdf_mask_data => ram_mask_in,
|
||||
ddr2_dq => ddr2_dq,
|
||||
ddr2_a => ddr2_a,
|
||||
ddr2_ba => ddr2_ba,
|
||||
ddr2_ras_n => ddr2_ras_n,
|
||||
ddr2_cas_n => ddr2_cas_n,
|
||||
ddr2_we_n => ddr2_we_n,
|
||||
ddr2_cs_n => ddr2_cs_n,
|
||||
ddr2_odt => ddr2_odt,
|
||||
ddr2_cke => ddr2_cke,
|
||||
ddr2_dm => ddr2_dm,
|
||||
ddr2_dqs => ddr2_dqs,
|
||||
ddr2_dqs_n => ddr2_dqs_n,
|
||||
ddr2_ck => ddr2_ck,
|
||||
ddr2_ck_n => ddr2_ck_n
|
||||
);
|
||||
|
||||
--~ sys_clk_p : in std_logic;
|
||||
--~ sys_clk_n : in std_logic;
|
||||
--~ clk200_p : in std_logic;
|
||||
--~ clk200_n : in std_logic;
|
||||
--~ sys_rst_n : in std_logic;
|
||||
|
||||
--~ rst0_tb : out std_logic;
|
||||
--~ clk0_tb : out std_logic;
|
||||
|
||||
--~ phy_init_done : out std_logic;
|
||||
|
||||
--~ app_wdf_afull : out std_logic;
|
||||
--~ app_af_afull : out std_logic;
|
||||
--~ app_wdf_wren : in std_logic;
|
||||
--~ app_af_wren : in std_logic;
|
||||
--~ app_af_addr : in std_logic_vector(30 downto 0);
|
||||
--~ app_af_cmd : in std_logic_vector(2 downto 0);
|
||||
--~ app_wdf_data : in std_logic_vector(127 downto 0);
|
||||
--~ app_wdf_mask_data : in std_logic_vector(15 downto 0);
|
||||
--~ rd_data_fifo_out : out std_logic_vector(127 downto 0);
|
||||
--~ rd_data_valid : out std_logic;
|
||||
|
||||
--~ ddr2_dq : inout std_logic_vector(63 downto 0);
|
||||
--~ ddr2_a : out std_logic_vector(12 downto 0);
|
||||
--~ ddr2_ba : out std_logic_vector(1 downto 0);
|
||||
--~ ddr2_ras_n : out std_logic;
|
||||
--~ ddr2_cas_n : out std_logic;
|
||||
--~ ddr2_we_n : out std_logic;
|
||||
--~ ddr2_cs_n : out std_logic_vector(0 downto 0);
|
||||
--~ ddr2_odt : out std_logic_vector(0 downto 0);
|
||||
--~ ddr2_cke : out std_logic_vector(0 downto 0);
|
||||
--~ ddr2_dm : out std_logic_vector(7 downto 0);
|
||||
--~ ddr2_dqs : inout std_logic_vector(7 downto 0);
|
||||
--~ ddr2_dqs_n : inout std_logic_vector(7 downto 0);
|
||||
--~ ddr2_ck : out std_logic_vector(1 downto 0);
|
||||
--~ ddr2_ck_n : out std_logic_vector(1 downto 0)
|
||||
|
||||
end rtl;
|
||||
|
||||
1
src/terminal
Submodule
1
src/terminal
Submodule
Submodule src/terminal added at 3fbc5a72c1
Reference in New Issue
Block a user