This website requires JavaScript.
Explore
Help
Sign In
riscv
/
workstation
Watch
1
Star
0
Fork
0
You've already forked workstation
Code
Issues
Pull Requests
Releases
Wiki
Activity
9
Commits
1
Branch
1
Tag
ce76d77699bdabbb1b7ec4fa05515c8e0383d6bb
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Klemens Schölhorn
ce76d77699
Add missing module to the ISE project and ignore generated MIG-Core
2018-06-05 17:15:48 +02:00
freedom
@
2c74ef7f03
Import freedom repos as submodules
2018-06-05 15:11:52 +02:00
freedom-u-sdk
@
0e61cba991
Import freedom repos as submodules
2018-06-05 15:11:52 +02:00
project
/ise
Add missing module to the ISE project and ignore generated MIG-Core
2018-06-05 17:15:48 +02:00
src
Import main constraints file
2018-06-05 16:04:27 +02:00
.gitmodules
Import terminal as a submodule
2018-06-05 15:33:43 +02:00
Description
RISC-V Linux-Workstation auf dem ML507
332
KiB
Languages
Verilog
37%
VHDL
36%
Diff
27%
