riscv
/
workstation
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
RISC-V Linux-Workstation auf dem ML507
9 Commits 1 Branch 1 Tag 332 KiB
Verilog 37%
VHDL 36%
Diff 27%
Go to file
Klemens Schölhorn ce76d77699 Add missing module to the ISE project and ignore generated MIG-Core 2018-06-05 17:15:48 +02:00
freedom@2c74ef7f03 Import freedom repos as submodules 2018-06-05 15:11:52 +02:00
freedom-u-sdk@0e61cba991 Import freedom repos as submodules 2018-06-05 15:11:52 +02:00
project/ise Add missing module to the ISE project and ignore generated MIG-Core 2018-06-05 17:15:48 +02:00
src Import main constraints file 2018-06-05 16:04:27 +02:00
.gitmodules Import terminal as a submodule 2018-06-05 15:33:43 +02:00