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Import main constraints file

This commit is contained in:
Klemens Schölhorn 2018-06-05 15:58:54 +02:00
parent 55cd91d4da
commit ea067af1ac
1 changed files with 70 additions and 0 deletions
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NET "sys_clock" LOC = AH15;
NET "sys_clock" PERIOD = 100 MHz HIGH 50%;
NET "ddr_clock_p" LOC = L19 | DIFF_TERM = TRUE;
NET "ddr_clock_n" LOC = K19 | DIFF_TERM = TRUE;
NET "ddr_clock_p" TNM_NET = "CLK_200";
TIMESPEC "TS_CLK_200" = PERIOD "CLK_200" 5 ns HIGH 50%;
# ddr_clock_n period doesn't need to be specified
NET "reset" LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI, Center
NET "clock_led" LOC="AG12"; # LED South
NET "reset_led" LOC="E8"; # LED Center
NET "uart_rx" LOC="AG15";
NET "uart_tx" LOC="AG20";
NET "led_0" LOC = H18; # no DCI
NET "led_1" LOC = L18; # no DCI
NET "led_2" LOC = G15; # no DCI
NET "led_3" LOC = AD26 | IOSTANDARD = LVCMOS18;
NET "led_4" LOC = G16; # no DCI
NET "led_5" LOC = AD25 | IOSTANDARD = LVCMOS18;
NET "led_6" LOC = AD24 | IOSTANDARD = LVCMOS18;
NET "led_7" LOC = AE24 | IOSTANDARD = LVCMOS18;
NET "dip_0" LOC="U25" | IOSTANDARD = LVCMOS18;
NET "dip_1" LOC="AG27" | IOSTANDARD = LVCMOS18;
NET "dip_2" LOC="AF25" | IOSTANDARD = LVCMOS18;
NET "dip_3" LOC="AF26" | IOSTANDARD = LVCMOS18;
NET "dip_4" LOC="AE27" | IOSTANDARD = LVCMOS18;
NET "dip_5" LOC="AE26" | IOSTANDARD = LVCMOS18;
NET "dip_6" LOC="AC25" | IOSTANDARD = LVCMOS18;
NET "dip_7" LOC="AC24" | IOSTANDARD = LVCMOS18;
# HDR1 2–12
NET "sdio_clk" LOC="H33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "sdio_cmd" LOC="F34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "sdio_dat[3]" LOC="H34"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "sdio_dat[2]" LOC="G33"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "sdio_dat[1]" LOC="G32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "sdio_dat[0]" LOC="H32"; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
# HDR1 14–20
NET "jtag_TCK" LOC="J32" | PULLUP | CLOCK_DEDICATED_ROUTE = FALSE; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "jtag_TMS" LOC="J34" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "jtag_TDI" LOC="L33" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET "jtag_TDO" LOC="M32" | PULLUP; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
# Termial DVI
NET "dvi_d(0)" LOC = AB8;
NET "dvi_d(1)" LOC = AC8;
NET "dvi_d(2)" LOC = AN12;
NET "dvi_d(3)" LOC = AP12;
NET "dvi_d(4)" LOC = AA9;
NET "dvi_d(5)" LOC = AA8;
NET "dvi_d(6)" LOC = AM13;
NET "dvi_d(7)" LOC = AN13;
NET "dvi_d(8)" LOC = AA10;
NET "dvi_d(9)" LOC = AB10;
NET "dvi_d(10)" LOC = AP14;
NET "dvi_d(11)" LOC = AN14;
NET "dvi_clk_p" LOC = AL11;
NET "dvi_clk_n" LOC = AL10;
NET "dvi_hsync" LOC = AM12;
NET "dvi_vsync" LOC = AM11;
NET "dvi_de" LOC = AE8;
NET "dvi_reset" LOC = AK6;
NET "dvi_i2c_scl" LOC = U27 | IOSTANDARD = LVCMOS18;
NET "dvi_i2c_sda" LOC = T29 | IOSTANDARD = LVCMOS18;