Wesley W. Terpstra and GitHub
64bff44462
Merge pull request #4 from sifive/periphery-keys
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DTS
2017-03-02 21:00:44 -08:00
Wesley W. Terpstra and Henry Cook
46aa6b0ac4
devices: include DTS meta-data
2017-03-02 20:39:30 -08:00
Wesley W. Terpstra and Henry Cook
baccd5ada2
devices: create periphery keys for all devices
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Standardize how they are connected to the periphery bus
2017-03-02 20:39:25 -08:00
Wesley W. Terpstra
88e4c8ee20
xilinx mig: track changes in rocket-chip
2017-02-03 18:17:58 -08:00
Wesley W. Terpstra
c010a1557a
sifive-blocks: trust diplomacy to get names right
2017-02-01 13:53:54 -08:00
Wesley W. Terpstra
535be3e976
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
5b6760394d
xilinx ip: adjust to new diplomacy API
2017-01-30 11:33:30 -08:00
Wesley W. Terpstra
d61d86e084
xilinx pcie: put buffers before the outputs to the controller
2017-01-20 22:38:27 -08:00
Wesley W. Terpstra
c68e44ec55
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
Wesley W. Terpstra
45c491cd69
LazyModule: provide Parameters
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This tracks PR #478 in rocketchip.
2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186
xilinx pcie: bytes, not bits
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This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
2016-12-06 16:13:12 -08:00
Wesley W. Terpstra
ca7555bd4d
RegMapFIFO: amoor.w can do thread-safe TX
2016-12-02 17:48:17 -08:00
Wesley W. TerpstraandGitHub
